公开(公告)号：US20070233937A1

公开(公告)日：2007-10-04

申请号：US11396262

申请日：2006-03-31

申请人： Richard Coulson ,  Gianpaolo Spadini ,  Neal Mielke

发明人： Richard Coulson ,  Gianpaolo Spadini ,  Neal Mielke

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F2212/2022

摘要： In one embodiment, the present invention includes a method for writing data into both a volatile portion and an erase block of a non-volatile portion of a storage device, and maintaining the data in the volatile portion until the data is successfully written to the erase block. In this way, enhanced data reliability is provided. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于将数据写入到存储设备的非易失性部分的易失性部分和擦除块中并将数据保持在易失性部分中直到数据成功写入擦除的方法 块。 以这种方式，提供了增强的数据可靠性。 描述和要求保护其他实施例。

公开(公告)号：US08595422B2

公开(公告)日：2013-11-26

申请号：US13546876

申请日：2012-07-11

申请人： Paul Ruby ,  Neal Mielke

发明人： Paul Ruby ,  Neal Mielke

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

公开(公告)号：US08230158B2

公开(公告)日：2012-07-24

申请号：US12190482

申请日：2008-08-12

申请人： Paul Ruby ,  Neal Mielke

发明人： Paul Ruby ,  Neal Mielke

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

公开(公告)号：US06943071B2

公开(公告)日：2005-09-13

申请号：US10162173

申请日：2002-06-03

申请人： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

发明人： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/11526 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/66825 ,  H01L29/7883

摘要： A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

摘要翻译： 一种非易失性存储单元，包括形成在衬底中并限定衬底有源区的一对间隔开的浅沟槽隔离区。 隧道电介质形成在衬底有源区上。 浮动栅极形成在隧道电介质上，并且在间隔开的浅沟槽隔离区域之间自对准。 介电层形成在浮栅上，形成在电介质层上的控制栅。 源极区域和漏极区域形成在浮置栅极的相对侧上的衬底有源区域中。

公开(公告)号：US06518618B1

公开(公告)日：2003-02-11

申请号：US09454683

申请日：1999-12-03

申请人： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

发明人： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

IPC分类号： H01L2972

CPC分类号： H01L27/11526 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/66825 ,  H01L29/7883

摘要： A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

公开(公告)号：US20120275221A1

公开(公告)日：2012-11-01

申请号：US13546876

申请日：2012-07-11

申请人： Paul Ruby ,  Neal Mielke

发明人： Paul Ruby ,  Neal Mielke

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已经被存储在存储块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

公开(公告)号：US20100039860A1

公开(公告)日：2010-02-18

申请号：US12190482

申请日：2008-08-12

申请人： Paul Ruby ,  Neal Mielke

发明人： Paul Ruby ,  Neal Mielke

IPC分类号： G11C16/04 ,  G11C16/06 ,  G06F7/58 ,  G11C8/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

公开(公告)号：US5566194A

公开(公告)日：1996-10-15

申请号：US471139

申请日：1995-06-06

申请人： Steven Wells ,  Neal Mielke

发明人： Steven Wells ,  Neal Mielke

IPC分类号： G11C16/32 ,  G11C29/00 ,  G06F11/00

CPC分类号： G11C29/88 ,  G11C16/32

摘要： Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

公开(公告)号：US5452311A

公开(公告)日：1995-09-19

申请号：US969756

申请日：1992-10-30

申请人： Steven Wells ,  Neal Mielke

发明人： Steven Wells ,  Neal Mielke

IPC分类号： G11C16/32 ,  G11C29/00 ,  G06F11/00

CPC分类号： G11C29/88 ,  G11C16/32

摘要： Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

摘要翻译： 用于控制存储器阵列的输出电路在锁存输出数据之前的时间段的长度的装置，包括用于检测从存储器阵列读取的数据中存在错误的装置，用于提供第一值以确定等待的装置 周期，响应于检测用于提供第二值的错误的装置，响应于第一值的装置，用于产生用于在第一时段之后产生从存储器阵列输出的数据的信号，并响应于第二值产生信号， 在第二个周期之后锁存来自存储器阵列的数据输出。

公开(公告)号：US5327383A

公开(公告)日：1994-07-05

申请号：US871485

申请日：1992-04-21

申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C29/82 ,  G11C16/10 ,  G11C16/16

摘要： Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

摘要翻译： 描述用于独立地控制闪存的擦除的电路，包括用于替换存储器阵列内的短路行的冗余行。 擦除命令将触发一个定序器电路，该电路对执行擦除事件任务的控制器进行调度。 通过嵌套擦除事件的控制，定序器电路允许轻松修改擦除事件。 定序器电路在接收到擦除命令时触发前提条件控制器。 前置条件控制器然后管理存储器阵列的预处理，包括短路行内的存储器单元。 前提条件控制器通过禁用用冗余行替换短路行来做到这一点。 在预处理期间，在存储单元被擦除为逻辑1之前，每个存储器单元被编程为逻辑0，以防止在后续擦除期间存储器单元的过度擦写。 之后，序列发生器触发擦除控制器。 然后擦除控制电路管理擦除。 电路还包括后置条件控制器和程序控制器。