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    Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy
    1.
    发明授权
    Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy 失效
    用于擦除结合行冗余的非易失性半导体存储器的方法和电路

    公开(公告)号：US5327383A

    公开(公告)日：1994-07-05

    申请号：US871485

    申请日：1992-04-21

    申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00 ,  G11C7/02

    CPC分类号： G11C29/82 ,  G11C16/10 ,  G11C16/16

    摘要： Circuitry for independently controlling the erasure of a flash memory including redundant rows for replacing shorted rows within the memory array is described. An erase command fires a sequencer circuit, which schedules the controllers that execute the tasks of an erase event. By nesting the control of erase events, the sequencer circuit allows easy modification of erase events. The sequencer circuit fires a precondition controller upon receipt of an erase command. The precondition controller then manages the preconditioning of the memory array, including memory cells within shorted rows. The precondition controller does so by disabling the replacement of shorted rows with redundant rows. During preconditioning each memory cell is programmed to a logic 0, before the memory cell is erased to a logic 1, to prevent the overerasure of memory cells during subsequent erasure. Afterward, the sequencer fires the erase controller. The erase control circuit then manages erasure. The circuitry also includes a postcondition controller and a program controller.

    摘要翻译： 描述用于独立地控制闪存的擦除的电路，包括用于替换存储器阵列内的短路行的冗余行。 擦除命令将触发一个定序器电路，该电路对执行擦除事件任务的控制器进行调度。 通过嵌套擦除事件的控制，定序器电路允许轻松修改擦除事件。 定序器电路在接收到擦除命令时触发前提条件控制器。 前置条件控制器然后管理存储器阵列的预处理，包括短路行内的存储器单元。 前提条件控制器通过禁用用冗余行替换短路行来做到这一点。 在预处理期间，在存储单元被擦除为逻辑1之前，每个存储器单元被编程为逻辑0，以防止在后续擦除期间存储器单元的过度擦写。 之后，序列发生器触发擦除控制器。 然后擦除控制电路管理擦除。 电路还包括后置条件控制器和程序控制器。

    Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
    2.
    发明授权
    Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy 失效
    用于预处理包含行冗余的非易失性半导体存储器中的短路行的方法和电路

    公开(公告)号：US5377147A

    公开(公告)日：1994-12-27

    申请号：US105871

    申请日：1993-08-11

    申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

    CPC分类号： G11C29/82 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

    摘要： Circuitry for verifying the preconditioning of shorted cells within a flash memory cell. The preconditioning circuitry accommodates shorted cells, allowing them to pass verification at lower threshold voltage levels than good cells but ensuring the threshold voltage levels of shorted cells are high enough to prevent bitline leakage. The circuitry includes a sense amplifier for comparing the threshold voltage of a memory cell within the memory array to a selected reference threshold voltage level. The sense amplifier indicates whether the array memory cells exceeds the selected reference threshold voltage level. Selection circuitry couples two different reference cells to the sense amplifier, each having a different threshold voltage level. One of the reference cells has a normal threshold voltage level; i.e., a threshold voltage level to which good cells should be preconditioned. The other reference cell, a shorted reference cell, has a threshold voltage less than the nominal threshold voltage, but sufficient to prevent the quick overerasure of array cells during erasure. When the array cell is shorted to another cell within the array, selection circuitry selects the shorted reference cell. Otherwise, the other reference cell is selected.

    摘要翻译： 用于验证闪存单元内的短路单元的预处理的电路。 预处理电路容纳短路单元，允许它们在比较好的单元更低的阈值电压电平下通过验证，但是确保短路单元的阈值电压电平足够高以防止位线泄漏。 该电路包括读出放大器，用于将存储器阵列内的存储单元的阈值电压与选定的参考阈值电压电平进行比较。 读出放大器指示阵列存储单元是否超过选定的参考阈值电压电平。 选择电路将两个不同的参考单元耦合到读出放大器，每个具有不同的阈值电压电平。 一个参考单元具有正常的阈值电压电平; 即要预处理好电池的阈值电压电平。 另一个参考单元，短路参考单元，具有小于标称阈值电压的阈值电压，但足以防止在擦除期间阵列单元的快速过渡。 当阵列单元与阵列内的另一单元短路时，选择电路选择短路参考单元。 否则，选择另一个参考单元。

    Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
    3.
    发明授权
    Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy 失效
    用于预处理包含行冗余的非易失性半导体存储器中的短路行的方法和电路

    公开(公告)号：US5347489A

    公开(公告)日：1994-09-13

    申请号：US871848

    申请日：1992-04-21

    申请人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    发明人： Amit Merchant ,  Mickey L. Fandrich ,  Neal Mielke

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

    CPC分类号： G11C29/82 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

    摘要： A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.

    摘要翻译： 描述了一种对存储器阵列的短行内的存储单元进行预处理和验证预处理的方法。 预处理开始于将预处理脉冲应用于短路在一起的两个存储单元。 之后，通过对两个短路存储器单元的栅极施加标称栅极电压电平来读取两个短路单元之一。 同时，通过向其栅极施加小于额定栅极电压电平的电压电平来读取短路参考电池。 当读取电压被施加到阵列单元和短路参考单元时，将两个短路阵列单元之一的阈值电压与短路参考单元的阈值电压进行比较。 短路参考电池具有低于预处理通常所需的电平的阈值电压电平，但足以防止短路存储器单元的快速过热。

    Memory devices and methods of storing data on a memory device
    5.
    发明授权
    Memory devices and methods of storing data on a memory device 有权
    存储器件和将数据存储在存储器件上的方法

    公开(公告)号：US08595422B2

    公开(公告)日：2013-11-26

    申请号：US13546876

    申请日：2012-07-11

    申请人： Paul Ruby ,  Neal Mielke

    发明人： Paul Ruby ,  Neal Mielke

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

    摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

    摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

    Memory devices and methods of storing data on a memory device
    6.
    发明授权
    Memory devices and methods of storing data on a memory device 有权
    存储器件和将数据存储在存储器件上的方法

    公开(公告)号：US08230158B2

    公开(公告)日：2012-07-24

    申请号：US12190482

    申请日：2008-08-12

    申请人： Paul Ruby ,  Neal Mielke

    发明人： Paul Ruby ,  Neal Mielke

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

    摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

    摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

    MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE
    9.
    发明申请
    MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE 有权
    存储器件和存储器件中的数据存储方法

    公开(公告)号：US20120275221A1

    公开(公告)日：2012-11-01

    申请号：US13546876

    申请日：2012-07-11

    申请人： Paul Ruby ,  Neal Mielke

    发明人： Paul Ruby ,  Neal Mielke

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

    摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

    摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已经被存储在存储块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。

    MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE
    10.
    发明申请
    MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE 有权
    存储器件和存储器件中的数据存储方法

    公开(公告)号：US20100039860A1

    公开(公告)日：2010-02-18

    申请号：US12190482

    申请日：2008-08-12

    申请人： Paul Ruby ,  Neal Mielke

    发明人： Paul Ruby ,  Neal Mielke

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G06F7/58 ,  G11C8/00

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00 ,  G11C2211/5647

    摘要： Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of memory cells; and a data randomizer configured to randomly or pseudo-randomly change original data to be stored in the memory block to changed data. The original data is changed such that a pattern of data as stored in the memory block is different than what it would have been if the original data had been stored in the memory block during a write operation. This configuration can reduce or eliminate data pattern-dependent errors in data digits stored in memory cells.

    摘要翻译： 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个存储单元的存储块; 以及数据随机化器，被配置为随机地或伪随机地将要存储在存储器块中的原始数据改变为改变的数据。 原始数据被改变，使得存储在存储器块中的数据的模式与在写入操作期间原始数据已被存储在存储器块中的情况不同。 该配置可以减少或消除存储在存储单元中的数据数据中的数据模式相关错误。