公开(公告)号：US5652163A

公开(公告)日：1997-07-29

申请号：US357728

申请日：1994-12-13

申请人： Richard D. Schinella ,  Keith Chao

发明人： Richard D. Schinella ,  Keith Chao

IPC分类号： G03F7/20 ,  H01L27/02 ,  H01L21/82

CPC分类号： G03F7/70466 ,  G03F7/70433 ,  H01L27/0207

摘要： A method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated.

摘要翻译： 一种用于形成适用于制造具有亚微米尺寸的集成电路结构的大规模场的方法和装置。 该方法包括沿着形成非常大规模集成电路的功能部件的边界将大尺度场细分为多个子场。 因此，可以更容易地容纳功能部件之间的导电互连的数量和尺寸，从而将子场拼接成大规模场。

公开(公告)号：US06426286B1

公开(公告)日：2002-07-30

申请号：US09574804

申请日：2000-05-19

申请人： Richard D. Schinella ,  Valeriy Sukharev

发明人： Richard D. Schinella ,  Valeriy Sukharev

IPC分类号： H01L2128

CPC分类号： H01L21/76834 ,  H01L21/76802 ,  H01L21/76888

摘要： An interconnection system having a bottom metal layer that has a conduction layer with a sidewall and an overlying barrier layer. A lateral barrier layer is disposed adjacent the sidewall of the conduction layer, and an insulation layer is over the bottom metal layer. The insulation layer forms vias extending through the insulation layer to the bottom metal layer. A top metal layer extends through the vias to electrically contact the bottom metal layer. The overlying barrier layer and the lateral barrier layer are relatively resistant to interaction with the top metal layer as compared to the conduction layer.

摘要翻译： 具有底部金属层的互连系统，该底部金属层具有带有侧壁的导电层和上覆的势垒层。 横向阻挡层邻近导电层的侧壁设置，绝缘层位于底部金属层的上方。 绝缘层形成通过绝缘层延伸到底部金属层的通孔。 顶部金属层延伸穿过通孔以电接触底部金属层。 与导电层相比，上覆阻挡层和横向阻挡层相对于与顶部金属层的相互作用相对抗性。

公开(公告)号：US5827777A

公开(公告)日：1998-10-27

申请号：US718852

申请日：1996-09-24

申请人： Richard D. Schinella ,  Gobi R. Padmanabhan ,  Joseph M. Zelayeta

发明人： Richard D. Schinella ,  Gobi R. Padmanabhan ,  Joseph M. Zelayeta

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24975 ,  Y10T428/265 ,  Y10T428/31678

摘要： A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

摘要翻译： 提出了一种用于在集成电路中制造相对薄的氮化钛阻挡层的方法。 通过为半导体晶片提供覆盖有绝缘层的导电层，氮化钛层可用于钨插头互连。 对绝缘层进行图案化和蚀刻以形成接触孔或通孔。 一层钛沉积在晶片的表面上，包括通孔的侧壁和底部。 然后在钛层上形成相对薄的氮化钛层。 氮化钛层的形成包括通过含氮物质与钛层的反应来生长氮化钛。 氮化钛层防止下面的钛层与沉积在晶片上的随后的钨层反应以填充通孔。 然后蚀刻钨层，使得剩余的钨在导电层之间形成插头互连。

公开(公告)号：US5674774A

公开(公告)日：1997-10-07

申请号：US474794

申请日：1995-06-07

申请人： Nicholas F. Pasch ,  Ashok Kapoor ,  Richard D. Schinella

发明人： Nicholas F. Pasch ,  Ashok Kapoor ,  Richard D. Schinella

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/335

CPC分类号： H01L29/66575 ,  H01L21/2652 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/665 ,  H01L29/66545

摘要： Remote electrical contacts for a semiconductor are produced by depositing a polysilicon layer over the entire surface of a semiconductor device and removing a portion of the polysilicon layer by chemi-mechanical polishing. The resulting structure is thereby provided with electrically isolated areas of polysilicon which constitute remote electrical contacts for the semiconductor device. The polysilicon layer or the isolated areas of polysilicon can be salicided to provide very low resistivity. Either the polysilicon layer or the salicide layer can be subjected to ion implantation to provide LDD regions.

摘要翻译： 通过在半导体器件的整个表面上沉积多晶硅层并通过化学机械抛光去除多晶硅层的一部分来制造用于半导体的远程电触点。 所得到的结构由此提供构成用于半导体器件的远程电触点的电绝缘的多晶硅区域。 多晶硅层或多晶硅的隔离区域可以被水化以提供非常低的电阻率。 可以对多晶硅层或自对接硅化物层进行离子注入以提供LDD区域。

公开(公告)号：US06350700B1

公开(公告)日：2002-02-26

申请号：US09607512

申请日：2000-06-28

申请人： Richard D. Schinella ,  Wilbur G. Catabay ,  Philippe Schoenborn

发明人： Richard D. Schinella ,  Wilbur G. Catabay ,  Philippe Schoenborn

IPC分类号： H01L2100

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/31633 ,  H01L21/76813

摘要： A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.

公开(公告)号：US5600182A

公开(公告)日：1997-02-04

申请号：US378027

申请日：1995-01-24

申请人： Richard D. Schinella ,  Gobi R. Padmanabhan ,  Joseph M. Zelayeta

发明人： Richard D. Schinella ,  Gobi R. Padmanabhan ,  Joseph M. Zelayeta

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L29/54

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24975 ,  Y10T428/265 ,  Y10T428/31678

摘要： A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

摘要翻译： 提出了一种用于在集成电路中制造相对薄的氮化钛阻挡层的方法。 通过为半导体晶片提供覆盖有绝缘层的导电层，氮化钛层可用于钨插头互连。 对绝缘层进行图案化和蚀刻以形成接触孔或通孔。 一层钛沉积在晶片的表面上，包括通孔的侧壁和底部。 然后在钛层上形成相对薄的氮化钛层。 氮化钛层的形成包括通过含氮物质与钛层的反应来生长氮化钛。 氮化钛层防止下面的钛层与沉积在晶片上的随后的钨层反应以填充通孔。 然后蚀刻钨层，使得剩余的钨在导电层之间形成插塞互连。

公开(公告)号：US07020859B2

公开(公告)日：2006-03-28

申请号：US10452689

申请日：2003-06-02

申请人： Richard D. Schinella

发明人： Richard D. Schinella

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： H01L22/34 ,  H01L27/0203

摘要： A method of performing a characterization of an integrated circuit design that is customized during succeeding fabrication steps. The characterization is accomplished with respect to different levels of a processing parameter that is fixed during preceding fabrication steps. A wafer is processed through the preceding fabrication steps, including processing the wafer at at least one of the preceding fabrication steps using processing that produces the different levels of the processing parameter within different integrated circuits on the wafer. This produces a standardized characterization wafer. The standardized characterization wafer is processed through the succeeding fabrication steps using customized processing to produce a customized characterization wafer. The integrated circuits on the customized characterization wafer are tested to determine which of the different levels of the processing parameter produces integrated circuits having desired characteristics.

摘要翻译： 执行在后续制造步骤期间定制的集成电路设计的表征的方法。 关于在先前制造步骤期间固定的处理参数的不同级别来实现表征。 通过前述制造步骤处理晶片，包括使用在晶片上的不同集成电路内产生不同级别的处理参数的处理，在至少一个前述制造步骤处理晶片。 这产生了标准化的表征晶片。 标准化表征晶片通过后续制造步骤使用定制处理来生产定制的表征晶片。 测试定制表面晶片上的集成电路，以确定哪个不同级别的处理参数产生具有所需特性的集成电路。

公开(公告)号：US06518193B1

公开(公告)日：2003-02-11

申请号：US09802424

申请日：2001-03-09

申请人： Kiran Kumar ,  Zhihai Wang ,  Rudy Rios ,  Wilbur G. Catabay ,  Richard D. Schinella

发明人： Kiran Kumar ,  Zhihai Wang ,  Rudy Rios ,  Wilbur G. Catabay ,  Richard D. Schinella

IPC分类号： H01L21302

CPC分类号： H01L21/67167 ,  C23C14/566 ,  C23C16/4401 ,  H01L21/67017 ,  H01L21/67201 ,  H01L21/76802 ,  H01L21/76843

摘要： An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber. The substrate transfer chamber maintains a third environment of high cleanliness around the substrate, and transfers the substrate into more than one substrate processing chambers, where the substrate is selectively transferred into and out of the more than one substrate processing chambers without leaving the high cleanliness of the third environment. The substrate transfer chamber also selectively passes the substrate to the substrate pass through chamber when the substrate pass through chamber has formed the high cleanliness of the second environment. The substrate pass through chamber also receives the substrate from the substrate transfer chamber, and selectively passes the substrate to the substrate load chamber when the substrate load chamber has formed the intermediate cleanliness of the first environment. The substrate load chamber receives the substrate from the substrate pass through chamber, and selectively passes the substrate out of the substrate load chamber and into the ambient contaminant laden environment when the substrate load chamber is not open to the substrate pass through chamber.

公开(公告)号：US3945857A

公开(公告)日：1976-03-23

申请号：US570124

申请日：1975-04-21

申请人： Richard D. Schinella ,  Michael P. Anthony

发明人： Richard D. Schinella ,  Michael P. Anthony

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/00 ,  H01L27/082 ,  H01L21/26 ,  H01L21/20 ,  H01L21/265

CPC分类号： H01L27/0821 ,  H01L21/00 ,  H01L21/76205 ,  H01L21/8224 ,  H01L27/00 ,  Y10S148/053 ,  Y10S148/096 ,  Y10S148/106 ,  Y10S148/167

摘要： A double-diffused, lateral transistor structure is fabricated utilizing an etch resistant mask to provide self-aligning positional accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at least one substantially flat surface, and the structure includes at least one region of insulating material formed adjacent the flat surface, the top surface of the insulating material being substantially coplanar with said one surface. A collector is formed in the semiconductor material adjacent first portions of both the flat surface and the insulating material, while an emitter is formed in the semiconductor material adjacent second portions of both the flat surface and the insulating material. A base separates the collector from the emitter.

摘要翻译： 使用耐蚀刻掩模制造双扩散横向晶体管结构，以提供用于形成晶体管的有源区域的自对准位置精度。 横向结构包括具有至少一个基本上平坦表面的半导体材料，并且该结构包括邻近平坦表面形成的绝缘材料的至少一个区域，绝缘材料的顶表面与所述一个表面基本上共面。 在半导体材料中，与平坦表面和绝缘材料的第一部分相邻的半导体材料中形成集电极，同时在半导体材料中形成邻近平坦表面和绝缘材料的第二部分的发射极。 基极将集电极与发射极分开。