公开(公告)号：US06438037B1

公开(公告)日：2002-08-20

申请号：US09851773

申请日：2001-05-09

申请人： Richard Fastow ,  Xin Guo ,  Sameer S. Haddad

发明人： Richard Fastow ,  Xin Guo ,  Sameer S. Haddad

IPC分类号： G11C1606

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design in which the threshold voltage is compacted by erasing a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying at least one fast-erase memory cell; selectively soft-programming the memory cells; and erasing subsequent to selectively soft-programming.

摘要翻译： 具有紧凑阈值电压分布的快闪存储器设计和用于压缩闪速存储器设计的阈值电压的方法，其中阈值电压通过擦除多个存储器单元而被压缩，以将存储器单元的阈值电压基本上朝向中位数 擦除阈值电压; 验证至少一个快速擦除存储器单元; 选择性地软编程存储器单元; 并且在选择性软编程之后擦除。

公开(公告)号：US06878589B1

公开(公告)日：2005-04-12

申请号：US10431322

申请日：2003-05-06

申请人： Yue-Song He ,  Richard Fastow ,  Xin Guo

发明人： Yue-Song He ,  Richard Fastow ,  Xin Guo

IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66825 ,  H01L29/7885

摘要： A method and system for improving short channel effect on a floating gate device is disclosed. In one embodiment, a p-type implant is applied to a source side of the floating gate device. In addition, the present embodiment applies a p-type implant to a drain side of the floating gate device. The p-type implant to the drain side is performed at a different angle than the p-type implant to the source side. The p-type implant to the drain side is implanted to a greater depth than that of the p-type implant to the source side.

摘要翻译： 公开了一种用于改善对浮动栅极器件的短沟道效应的方法和系统。 在一个实施例中，p型注入被施加到浮动栅极器件的源极侧。 此外，本实施例将p型注入施加到浮动栅极器件的漏极侧。 以与植入源侧的p型植入物不同的角度进行到漏极侧的p型植入。 植入到漏极侧的p型植入物被深度植入到源极侧的p型植入物的深度。

公开(公告)号：US10542437B2

公开(公告)日：2020-01-21

申请号：US15775628

申请日：2016-11-23

申请人： Youping Zhao ,  Qixin Tai ,  Xin Guo ,  Chen Sun

发明人： Youping Zhao ,  Qixin Tai ,  Xin Guo ,  Chen Sun

IPC分类号： H04W16/14 ,  H04L27/00 ,  H04J11/00 ,  H04B7/0413 ,  H04B7/0456

摘要： A spectrum access method and an apparatus utilizing same. A spectrum management apparatus includes at least one processor configured to: determine location information and antenna angle information of each of at least one secondary apparatus; in response to a request for accessing an idle spectrum of a primary apparatus, determine, according to the location information and the antenna angle information of each of the at least one secondary apparatus, a secondary apparatus to grant access to the idle spectrum; and provide, to a serving base station of each of the secondary apparatuses having the access granted, the location information and the antenna angle information of all of the secondary apparatuses having the access granted, to enable the serving base station to perform interference alignment preceding.

公开(公告)号：US10356672B2

公开(公告)日：2019-07-16

申请号：US15544927

申请日：2016-01-25

申请人： Xin Guo ,  Yuxin Wei ,  Jinhui Chen ,  Chen Sun ,  SONY CORPORATION

发明人： Xin Guo ,  Yuxin Wei ,  Jinhui Chen ,  Chen Sun

IPC分类号： H04W4/00 ,  H04W36/00 ,  H04W24/00 ,  H04B17/309 ,  H04W76/23 ,  H04W4/02 ,  H04W36/24

摘要： An apparatus and a method in a wireless communication system. In the wireless communication system, a master device provides a data forwarding service for one or plural slave devices, a master device side apparatus including: a monitoring unit, configured to monitor a predetermined trigger event relating to a change in state of the master device; a handover pre-measurement control unit, configured to respond to the predetermined trigger event by controlling the handover pre-measurement of the one or plural slave devices; and a handover measurement control unit, configured to control, based on the handover pre-measurement results, the handover measurement of the one or plural slave devices. The apparatus and method can accelerate start time of effective link handover in a dynamic network, reduce unnecessary link handover, and reduce delays and data loss caused by link failure.

公开(公告)号：US10085259B2

公开(公告)日：2018-09-25

申请号：US14895167

申请日：2014-07-29

申请人： Chen Sun ,  Xin Guo

发明人： Chen Sun ,  Xin Guo

IPC分类号： H04W72/04 ,  H04W72/08 ,  H04W72/10 ,  H04W16/14

CPC分类号： H04W72/0453 ,  H04W16/14 ,  H04W72/082 ,  H04W72/10

摘要： A system that receives a request for resources from a first system of a plurality of systems having different levels of priority; identifies resources that are available in a second system different from the plurality of systems based on the received request; and determines whether to adjust a resource assigned to the plurality of systems based on the priority level of the first system and the resources that are available in the second system.

公开(公告)号：US20170139631A1

公开(公告)日：2017-05-18

申请号：US15377200

申请日：2016-12-13

申请人： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

发明人： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC分类号： G06F3/06

CPC分类号： G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

摘要： According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

公开(公告)号：US09268631B2

公开(公告)日：2016-02-23

申请号：US13976463

申请日：2012-03-29

申请人： Lark-Hoon Leem ,  Kiran Pangal ,  Xin Guo

发明人： Lark-Hoon Leem ,  Kiran Pangal ,  Xin Guo

IPC分类号： G06F11/00 ,  G11C29/00 ,  G06F11/08 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10

CPC分类号： G06F11/08 ,  G06F11/1048 ,  G11C11/5628 ,  G11C16/3418

摘要： Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed.

摘要翻译： 公开了用于生成或提供用于从包括在存储设备中的非易失性存储器的一个或多个存储器单元的读取错误中恢复的移动读取参考（MRR）表的示例。 可以将优先级自适应地分配给包括在MRR表中的条目，并且可以基于分配的优先级对条目进行排序使用。 其他的例子被描述和要求保护。

公开(公告)号：US09047187B2

公开(公告)日：2015-06-02

申请号：US13536861

申请日：2012-06-28

申请人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

发明人： Xin Guo ,  Yogesh B. Wakchaure ,  Kiran Pangal ,  Hiroyuki Sanda

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/10

CPC分类号： G06F11/073 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1016 ,  G06F11/1068

摘要： Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.

摘要翻译： 缺陷管理逻辑延长了存储系统的使用寿命。 例如，如本文所讨论的，故障检测逻辑检测存储器系统中的故障的发生。 缺陷管理逻辑确定失败的类型，例如失败是婴儿死亡型失败还是迟发型失败。 根据故障类型，缺陷管理逻辑执行不同的操作以延长存储系统的使用寿命。 例如，对于早期生活故障，缺陷管理逻辑可以将块的一部分包括故障退出。 对于后期生活故障，由于读取/写入过多，故障管理逻辑可以将故障块从第一位单元存储密度模式转换为以每位存储单元存储密度模式运行。

公开(公告)号：US08954650B2

公开(公告)日：2015-02-10

申请号：US13234446

申请日：2011-09-16

申请人： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

发明人： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C16/04 ,  G11C16/34

CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/3422

摘要： Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.

摘要翻译： 描述了用于改善非易失性存储器（NVM）的读取耐久性的装置，系统和方法。 该方法包括：确定对应于NVM块的读取计数; 识别NVM的块是否是部分编程块（PPB）; 当识别出块是PPB时，将读取计数与第一阈值进行比较; 并且当另外标识时，将读取计数与第二阈值进行比较，其中第一阈值小于第二阈值。 该方法还包括：识别作为PPB的块; 确定对应于PPB的未编程页面的第一字线; 以及将所述第一字线发送到所述NVM，其中所述NVM应用：对应于所述PPB的未编程页面的字线的第一读取电压电平和对应于所述PPB的编程页面的字线的第二读取电压电平 PPB。

公开(公告)号：US08914662B2

公开(公告)日：2014-12-16

申请号：US13258401

申请日：2009-09-17

申请人： Xin Guo ,  Hongjian Zhai ,  Chang Zhou ,  Hongqi Chen

发明人： Xin Guo ,  Hongjian Zhai ,  Chang Zhou ,  Hongqi Chen

IPC分类号： G06F1/12 ,  H04J3/06 ,  H04L12/26

CPC分类号： H04J3/0673 ,  G06F1/12 ,  H04J3/0638 ,  H04J3/0658 ,  H04J3/0661 ,  H04J3/0667 ,  H04J3/0682 ,  H04L43/0852 ,  H04L43/106

摘要： The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein the clock module is connected with the data identification module and the data correction module respectively, and used for providing clock information to the data identification module and the data correction module; the data identification module is used for receiving data and acquiring current time information from the clock module; and the data correction module is connected with the data identification module, and is used for accumulating a positive or negative value of the current time information with the time information included in the data according to an outputting direction of the data and outputting the accumulated time information together with the data. By adopting the present invention, the residence time information of the data in the switching node is acquired by a hardware device, and the time information included in the data is corrected according to the residence time information, so that the transparent clock of the data can be effectively implemented, and the acquired residence time information is of a high precision and is acquired stably.

摘要翻译： 本发明公开了一种实现透明时钟的装置和方法。 该装置包括：时钟模块，数据识别模块和数据校正模块，其中时钟模块分别与数据识别模块和数据校正模块连接，用于向数据识别模块和数据提供时钟信息 校正模块; 数据识别模块用于从时钟模块接收数据和获取当前时间信息; 并且数据校正模块与数据识别模块连接，并且用于根据数据的输出方向用包含在数据中的时间信息累积当前时间信息的正值或负值，并输出累积时间信息 连同数据。 通过采用本发明，通过硬件装置获取切换节点中的数据的停留时间信息，根据停留时间信息来校正包含在数据中的时间信息，使得数据的透明时钟可以 有效实施，获得的停留时间信息高精度，稳定获取。