公开(公告)号：US6140678A

公开(公告)日：2000-10-31

申请号：US962867

申请日：1997-11-03

申请人： Wayne B. Grabowski ,  Richard K. Williams ,  Mohamed N. Darwish

发明人： Wayne B. Grabowski ,  Richard K. Williams ,  Mohamed N. Darwish

IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/745

CPC分类号： H01L27/0255 ,  H01L29/1095 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0696

摘要： A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET. Specifications for a number of commercially acceptable devices are given.

摘要翻译： 功率MOSFET包括限定多个MOSFET单元的沟槽栅极。 产生保护性扩散，优选在非活性电池中，以形成与每个MOSFET单元中的沟道区并联连接的二极管。 保护性扩散取代了美国专利中教导的深部中心扩散。 5,072,266号文件防止了栅极沟槽角落附近的碰撞电离和载流子的产生，这可能损坏或破坏栅极氧化物层。 此外，二极管可以设计成具有限制栅极氧化物层两端的电场强度的击穿电压。 消除深的中心扩散允许增加电池密度并改善MOSFET的导通电阻。 给出了许多商业上可接受的装置的规格。

公开(公告)号：US07276411B2

公开(公告)日：2007-10-02

申请号：US11137001

申请日：2005-05-25

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L21/8242 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

公开(公告)号：US07282412B2

公开(公告)日：2007-10-16

申请号：US11137056

申请日：2005-05-25

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

摘要翻译： 诸如功率MOSFET的沟槽半导体器件通过增加沟槽底部的栅极氧化物层的厚度来减小沟槽拐角处的高电场。 描述了用于制造这种设备的几个过程。 在一组工艺中，在蚀刻沟槽之后进行氧化硅的定向沉积，在沟槽的底部产生厚的氧化物层。 沉积在沟槽壁上的任何氧化物在薄的栅极氧化物层生长在壁上之前被去除。 然后在多层或多层中填充沟槽。 在该方法的变化中，在蚀刻沟槽的壁之前，在沟槽底部的氧化物上沉积少量的光致抗蚀剂。 或者，多晶硅可以沉积在沟槽中并被回蚀，直到只有一部分保留在沟槽的底部。 然后将多晶硅氧化，并用多晶硅再填充沟槽。 该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。 形成“键孔”形栅电极的工艺包括在沟槽的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化的多晶硅，并用多晶硅填充沟槽。

公开(公告)号：US06277695B1

公开(公告)日：2001-08-21

申请号：US09293380

申请日：1999-04-16

申请人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

发明人： Richard K. Williams ,  Sung-Shan Tai ,  Dorman C. Pitzer ,  Wayne B. Grabowski ,  Anthony Tsui ,  Mike F. Chang

IPC分类号： H01L21336

CPC分类号： H01L29/66719 ,  H01L29/66712

摘要： The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

摘要翻译： 通过在MOSFET的栅极上制造侧壁间隔来形成垂直平面DMOSFET中的源极和体区的金属接触。 以这种方式将金属接触自对准到栅极，DMOSFET中的每个电池的横向尺寸可以显着减小，而不会有接触和栅极之间短路的风险，并且电池的堆积密度可以 增加。 以这种方式，可以实现装置的导通电阻的显着降低。

公开(公告)号：US06900100B2

公开(公告)日：2005-05-31

申请号：US10793089

申请日：2004-03-04

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

公开(公告)号：US06268242B1

公开(公告)日：2001-07-31

申请号：US09314621

申请日：1999-05-19

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L218234

CPC分类号： H03K17/163 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H01L2924/00

摘要： One or more diodes are connected in a conductive path between the source and gate of a vertical MOSFET to prevent the voltage between the gate and source from exceeding a predetermined level and thereby protect the gate oxide layer from damage. The diodes are formed in the same polysilicon layer that is used to form the gate of the MOSFET, by implanting N and P-type dopants into the layer. To minimize the number of additional processing steps required, at least one of these implants is performed simultaneously with the implanting of the source or body of the MOSFET. As an additional aspect of the invention, the metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

摘要翻译： 一个或多个二极管连接在垂直MOSFET的源极和栅极之间的导电路径中，以防止栅极和源极之间的电压超过预定水平，从而保护栅极氧化物层免受损坏。 二极管通过将N和P型掺杂剂注入该层而形成在用于形成MOSFET栅极的同一多晶硅层中。 为了最小化所需的附加处理步骤的数量，这些植入物中的至少一个与注入MOSFET的源或体同时进行。 作为本发明的另一方面，通过在MOSFET的栅极上制造侧壁间隔来形成垂直平面DMOSFET中的源极和体区的金属接触。 以这种方式将金属接触自对准到栅极，DMOSFET中的每个电池的横向尺寸可以显着减小，而不会有接触和栅极之间短路的风险，并且电池的堆积密度可以 增加。 以这种方式，可以实现装置的导通电阻的显着降低。

公开(公告)号：US06204533B1

公开(公告)日：2001-03-20

申请号：US09089250

申请日：1998-06-02

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7808 ,  H01L29/7827

摘要： A vertical trench-gated power MOSFET includes MOSFET cells in the shape of longitudinal stripes. The body diffusion of each cell contains a relatively heavily-doped region which extends parallel to the length of the cell and contacts an overlying metal source/body contact layer at specific locations. In one embodiment, the contact is made at an end of the cell. In another embodiment, the contact is made at intervals along the length of the cell. In addition, the power MOSFET contains diode cells placed at intervals in the array of cells. The diode cells contain diodes connected in parallel with the MOSFET cells and protect the gate oxide layer lining the trenches from damage due to large electric fields and hot carrier injection. By restricting the areas where the body contact is made and using the diode cells, the width of the MOSFET cells can be reduced substantially, thereby reducing the on-resistance of the power MOSFET.

摘要翻译： 垂直沟槽栅功率MOSFET包括纵向条纹形状的MOSFET单元。 每个单元的体扩散包含相对重掺杂的区域，其平行于单元的长度延伸并且在特定位置处接触覆盖的金属源/体接触层。 在一个实施例中，在电池的端部进行接触。 在另一个实施例中，沿着电池的长度间隔地进行接触。 另外，功率MOSFET还包含二极管单元间隔放置在单元阵列中。 二极管单元包含与MOSFET单元并联连接的二极管，并保护衬套沟槽的栅极氧化层免受大电场和热载流子注入的损害。 通过限制制造体接触的区域并使用二极管单元，可以大大降低MOSFET单元的宽度，从而降低功率MOSFET的导通电阻。

公开(公告)号：US07238568B2

公开(公告)日：2007-07-03

申请号：US11137151

申请日：2005-05-25

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L21/8242 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

公开(公告)号：US06291298B1

公开(公告)日：2001-09-18

申请号：US09318403

申请日：1999-05-25

申请人： Richard K. Williams ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Wayne B. Grabowski

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

摘要翻译： 诸如功率MOSFET的沟槽半导体器件通过增加沟槽底部的栅极氧化物层的厚度来减小沟槽拐角处的高电场。 描述了用于制造这种设备的几个过程。 在一组工艺中，在蚀刻沟槽之后进行氧化硅的定向沉积，在沟槽的底部产生厚的氧化物层。 沉积在沟槽壁上的任何氧化物在薄的栅极氧化物层生长在壁上之前被去除。 然后在多层或多层中填充沟槽。 在该方法的变化中，在蚀刻沟槽的壁之前，在沟槽底部的氧化物上沉积少量的光致抗蚀剂。 或者，多晶硅可以沉积在沟槽中并被回蚀，直到只有一部分保留在沟槽的底部。 然后将多晶硅氧化，并用多晶硅再填充沟槽。 该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。 形成“键孔”形栅电极的工艺包括在沟槽的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化的多晶硅，并用多晶硅填充沟槽。

公开(公告)号：US6078090A

公开(公告)日：2000-06-20

申请号：US832012

申请日：1997-04-02

申请人： Richard K. Williams ,  Shekar S. Malikarjunaswamy ,  Jacek Korec ,  Wayne B. Grabowski

发明人： Richard K. Williams ,  Shekar S. Malikarjunaswamy ,  Jacek Korec ,  Wayne B. Grabowski

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L27/095 ,  H01L29/872 ,  H01L29/48

CPC分类号： H01L29/872 ,  H01L27/0255 ,  H01L27/0727 ,  H01L27/095 ,  H01L29/8725

摘要： A trench-gated Schottky diode of the kind described in U.S. Pat. No. 5,365,102 is provided with an integral clamping diode which protects the gate oxide from damage from high electric fields and hot carrier generation when the device is reverse-biased. The clamping diode is arranged in parallel with the normal current path through the Schottky diode and comprises a PN junction created by a diffusion of opposite conductivity to the semiconductor material of the Schottky diode. In a preferred embodiment, the clamping diode is selected to prevent significant impact ionization near the trenched gate during either steady state- or deep depletion-induced avalanche breakdown.

摘要翻译： 美国专利中描述的沟槽门式肖特基二极管。 第5,365,102号设有集成的钳位二极管，当器件被反向偏置时，保护栅极氧化物免受高电场和热载流子产生的损害。 钳位二极管与通过肖特基二极管的正常电流路径平行布置，并且包括由与肖特基二极管的半导体材料相反的导电性的扩散产生的PN结。 在优选实施例中，选择钳位二极管以在稳态或深耗损诱导的雪崩击穿期间防止在沟槽栅极附近的显着的电离电离。