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    Trench-gated power MOSFET with protective diode
    1.
    发明授权
    Trench-gated power MOSFET with protective diode 失效
    带保护二极管的沟槽式功率MOSFET

    公开(公告)号：US6140678A

    公开(公告)日：2000-10-31

    申请号：US962867

    申请日：1997-11-03

    申请人： Wayne B. Grabowski ,  Richard K. Williams ,  Mohamed N. Darwish

    发明人： Wayne B. Grabowski ,  Richard K. Williams ,  Mohamed N. Darwish

    IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/745

    CPC分类号： H01L27/0255 ,  H01L29/1095 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0696

    摘要： A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET. Specifications for a number of commercially acceptable devices are given.

    摘要翻译： 功率MOSFET包括限定多个MOSFET单元的沟槽栅极。 产生保护性扩散，优选在非活性电池中，以形成与每个MOSFET单元中的沟道区并联连接的二极管。 保护性扩散取代了美国专利中教导的深部中心扩散。 5,072,266号文件防止了栅极沟槽角落附近的碰撞电离和载流子的产生，这可能损坏或破坏栅极氧化物层。 此外，二极管可以设计成具有限制栅极氧化物层两端的电场强度的击穿电压。 消除深的中心扩散允许增加电池密度并改善MOSFET的导通电阻。 给出了许多商业上可接受的装置的规格。

    Trench MOSFET with multi-resistivity drain to provide low on-resistance
    4.
    发明授权
    Trench MOSFET with multi-resistivity drain to provide low on-resistance 失效
    沟槽MOSFET具有多电阻漏极，提供低导通电阻

    公开(公告)号：US5895952A

    公开(公告)日：1999-04-20

    申请号：US701035

    申请日：1996-08-21

    申请人： Mohamed N. Darwish ,  Richard K. Williams

    发明人： Mohamed N. Darwish ,  Richard K. Williams

    IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/7813 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/0847

    摘要： A MOSFET switch with a gate formed in a trench has a drain which includes a region of relatively high resistivity adjacent the trench and a region of relatively low resistivity further away from the trench. The drain may also include a "delta" layer having even lower resistivity in a central region of the MOSFET cell. The high resistivity region limits the strength of the electric field at the edge of the trench (particularly where there are any sharp corners) and thereby avoids damage to the gate oxide layer. The central "delta" layer helps to insure that any breakdown will occur near the center of the MOSFET cell, away from the gate oxide, and to lower the resistance of the MOSFET when it is in an on condition.

    摘要翻译： 具有形成在沟槽中的栅极的MOSFET开关具有漏极，该漏极包括邻近沟槽的相对高电阻率的区域和远离沟槽的相对低电阻率的区域。 漏极还可以包括在MOSFET电池的中心区域中具有甚至更低电阻率的“delta”层。 高电阻率区域限制了沟槽边缘处的电场强度（特别是在任何尖角处），从而避免了对栅极氧化物层的损伤。 中央“三角洲”层有助于确保在MOSFET单元的中心附近发生任何击穿，远离栅极氧化物，并且在其处于导通状态时降低MOSFET的电阻。

    Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
    5.
    发明授权
    Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer 失效
    制造具有多电阻率漏极的沟槽MOSFET的方法，通过改变外延层中的掺杂剂浓度来提供低导通电阻

    公开(公告)号：US5674766A

    公开(公告)日：1997-10-07

    申请号：US429414

    申请日：1995-04-26

    申请人： Mohamed N. Darwish ,  Richard K. Williams

    发明人： Mohamed N. Darwish ,  Richard K. Williams

    IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/7813 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/0847

    摘要： A MOSFET switch with a gate formed in a trench has a drain which includes a region of relatively high resistivity adjacent the trench and a region of relatively low resistivity further away from the trench. The drain may also include a "delta" layer having even lower resistivity in a central region of the MOSFET cell. The high resistivity region limits the strength of the electric field at the edge of the trench (particularly where there are any sharp corners) and thereby avoids damage to the gate oxide layer. The central "delta" layer helps to insure that any breakdown will occur near the center of the MOSFET cell, away from the gate oxide, and to lower the resistance of the MOSFET when it is in an on condition.

    摘要翻译： 具有形成在沟槽中的栅极的MOSFET开关具有漏极，该漏极包括邻近沟槽的相对高电阻率的区域和远离沟槽的相对低电阻率的区域。 漏极还可以包括在MOSFET电池的中心区域中具有甚至更低电阻率的“delta”层。 高电阻率区域限制了沟槽边缘处的电场强度（特别是在任何尖角处），从而避免了对栅极氧化物层的损伤。 中央“三角洲”层有助于确保在MOSFET单元的中心附近发生任何击穿，远离栅极氧化物，并且在其处于导通状态时降低MOSFET的电阻。

    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
    6.
    发明授权
    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same 有权

    公开(公告)号：US07276411B2

    公开(公告)日：2007-10-02

    申请号：US11137001

    申请日：2005-05-25

    申请人： Richard K. Williams ,  Wayne B. Grabowski

    发明人： Richard K. Williams ,  Wayne B. Grabowski

    IPC分类号： H01L21/8242 ,  H01L21/76

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

    摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same
    7.
    发明授权
    Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same 有权
    具有多个厚度的栅极氧化物层的沟槽半导体器件及其制造方法

    公开(公告)号：US07282412B2

    公开(公告)日：2007-10-16

    申请号：US11137056

    申请日：2005-05-25

    申请人： Richard K. Williams ,  Wayne B. Grabowski

    发明人： Richard K. Williams ,  Wayne B. Grabowski

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

    摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

    摘要翻译： 诸如功率MOSFET的沟槽半导体器件通过增加沟槽底部的栅极氧化物层的厚度来减小沟槽拐角处的高电场。 描述了用于制造这种设备的几个过程。 在一组工艺中，在蚀刻沟槽之后进行氧化硅的定向沉积，在沟槽的底部产生厚的氧化物层。 沉积在沟槽壁上的任何氧化物在薄的栅极氧化物层生长在壁上之前被去除。 然后在多层或多层中填充沟槽。 在该方法的变化中，在蚀刻沟槽的壁之前，在沟槽底部的氧化物上沉积少量的光致抗蚀剂。 或者，多晶硅可以沉积在沟槽中并被回蚀，直到只有一部分保留在沟槽的底部。 然后将多晶硅氧化，并用多晶硅再填充沟槽。 该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。 形成“键孔”形栅电极的工艺包括在沟槽的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化的多晶硅，并用多晶硅填充沟槽。

    Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact
    10.
    发明授权
    Method of forming vertical mosfet device having voltage clamped gate and self-aligned contact 有权
    形成具有电压钳位门和自对准触点的垂直mosfet器件的方法

    公开(公告)号：US06268242B1

    公开(公告)日：2001-07-31

    申请号：US09314621

    申请日：1999-05-19

    申请人： Richard K. Williams ,  Wayne B. Grabowski

    发明人： Richard K. Williams ,  Wayne B. Grabowski

    IPC分类号： H01L218234

    CPC分类号： H03K17/163 ,  H01L2924/0002 ,  H03K17/04123 ,  H03K17/08122 ,  H01L2924/00

    摘要： One or more diodes are connected in a conductive path between the source and gate of a vertical MOSFET to prevent the voltage between the gate and source from exceeding a predetermined level and thereby protect the gate oxide layer from damage. The diodes are formed in the same polysilicon layer that is used to form the gate of the MOSFET, by implanting N and P-type dopants into the layer. To minimize the number of additional processing steps required, at least one of these implants is performed simultaneously with the implanting of the source or body of the MOSFET. As an additional aspect of the invention, the metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

    摘要翻译： 一个或多个二极管连接在垂直MOSFET的源极和栅极之间的导电路径中，以防止栅极和源极之间的电压超过预定水平，从而保护栅极氧化物层免受损坏。 二极管通过将N和P型掺杂剂注入该层而形成在用于形成MOSFET栅极的同一多晶硅层中。 为了最小化所需的附加处理步骤的数量，这些植入物中的至少一个与注入MOSFET的源或体同时进行。 作为本发明的另一方面，通过在MOSFET的栅极上制造侧壁间隔来形成垂直平面DMOSFET中的源极和体区的金属接触。 以这种方式将金属接触自对准到栅极，DMOSFET中的每个电池的横向尺寸可以显着减小，而不会有接触和栅极之间短路的风险，并且电池的堆积密度可以 增加。 以这种方式，可以实现装置的导通电阻的显着降低。