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    Programmable delay generator and application circuits having said delay generator
    5.
    发明授权
    Programmable delay generator and application circuits having said delay generator 有权
    具有所述延迟发生器的可编程延迟发生器和应用电路

    公开(公告)号：US06188261B1

    公开(公告)日：2001-02-13

    申请号：US09233427

    申请日：1999-01-20

    申请人： Hideyuki Nosaka ,  Akira Minakawa ,  Yo Yamaguchi ,  Akihiro Yamagishi

    发明人： Hideyuki Nosaka ,  Akira Minakawa ,  Yo Yamaguchi ,  Akihiro Yamagishi

    IPC分类号： H03K301

    CPC分类号： H03L7/081 ,  G06F1/025 ,  G06F7/68 ,  H03K4/502 ,  H03K5/00006 ,  H03K5/131 ,  H03K5/135 ,  H03K5/156 ,  H03L7/18 ,  H03L2207/10 ,  H03M1/822

    摘要： A programmable delay generator comprises a first ramp wave generator and a second ramp wave generator, each having the same structure as each other, each of them operating with external common clock pulses, and each of them providing potential gradient and final potential incorporated with an external set data; a comparator for comparing an output (Vs) of the first ramp wave generator and an output (Vk) of the second ramp wave generator so that an output pulse is provided when the outputs of two ramp wave generators coincide with each other; said first ramp wave generator providing a first ramp voltage (Vs) upon receipt of a first set data (S) at a predetermined time (t0); said second ramp wave generator providing a threshold voltage (Vk) upon receipt of a second set data (K) at a time which preceds at least one clock time (T) than said predetermined time (t0); said comparator providing an output pulse delayed by delay time (td) which is proportional to ratio (K/S) of said second set data (K) and said first set data (S) from said predetermined time. An application circuit using said programmable delay generator, including a frequency synthesizer, a frequency multiplier, a duty ratio converter, and a PLL frequency synthesizer is also provided.

    摘要翻译： 可编程延迟发生器包括第一斜坡波发生器和第二斜波发生器，每个具有彼此相同的结构，它们中的每一个以外部公共时钟脉冲进行操作，并且它们中的每一个提供与外部 设置数据; 比较器，用于比较第一斜坡波发生器的输出（Vs）和第二斜坡波发生器的输出（Vk），使得当两个斜波发生器的输出彼此一致时提供输出脉冲; 所述第一斜坡波发生器在预定时间（t0）接收到第一设定数据（S）时提供第一斜坡电压（Vs）; 所述第二斜波发生器在比所述预定时间（t0）至少一个时钟时间（T）之前的时间接收到第二设置数据（K）时提供阈值电压（Vk）; 所述比较器提供延迟延迟时间（td）的输出脉冲，该延迟时间（td）与所述第二设定数据（K）和所述第一设定数据（S）的比率（K / S）成比例。 还提供了使用包括频率合成器，倍频器，占空比转换器和PLL频率合成器的所述可编程延迟发生器的应用电路。

    Current-switching cell and digital-to-analog converter
    6.
    发明授权
    Current-switching cell and digital-to-analog converter 有权
    电流开关单元和数模转换器

    公开(公告)号：US08493257B2

    公开(公告)日：2013-07-23

    申请号：US13145782

    申请日：2010-01-28

    申请人： Munehiko Nagatani ,  Hideyuki Nosaka ,  Shogo Yamanaka ,  Kimikazu Sano ,  Koichi Murata

    发明人： Munehiko Nagatani ,  Hideyuki Nosaka ,  Shogo Yamanaka ,  Kimikazu Sano ,  Koichi Murata

    IPC分类号： H03M1/66

    CPC分类号： H03M1/662 ,  H03M1/742

    摘要： Two D flip-flops (D-FFMA, D-FFMB) output two half-rate signals (DMR-A, DMR-B) by dividing a digital input signal (DM) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (SM1, SM2) are driven by the two half-rate signals (DMR-A, DMR-B). Third and fourth switches (SM3, SM4) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).

    摘要翻译： 两个D触发器（D-FFMA，D-FFMB）通过将数字输入信号（DM）分成两个信号并基于时钟信号重新定时（DMR-A，D-FFMB）输出两个半速率信号 CLK）和负相位时钟信号（CLKB）。 第一和第二开关（SM1，SM2）由两个半速率信号（DMR-A，DMR-B）驱动。 第三和第四开关（SM3，SM4）由与时钟信号（CLK）频率相同的频率的选择信号SW和负相位选择信号SWB驱动，但与时钟信号（CLK ）。 因此，从电流源（1）提供给负载（4）的电流成为与时钟信号（CLK）的频率的两倍的转换频率相对应的电流信号。

    Automatic gain control circuit
    8.
    发明授权
    Automatic gain control circuit 有权
    自动增益控制电路

    公开(公告)号：US08593223B2

    公开(公告)日：2013-11-26

    申请号：US13527512

    申请日：2012-06-19

    申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Yasunobu Inabe ,  Eisuke Tsuchiya

    发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Yasunobu Inabe ,  Eisuke Tsuchiya

    IPC分类号： H03G3/10

    CPC分类号： H03G1/0023

    摘要： In an automatic gain control circuit, a peak detection circuit detects and outputs the peak voltage of an output signal from a variable gain circuit. An average value detection/output amplitude setting circuit detects the average value voltage of an output signal from the variable gain circuit, and outputs a calculated voltage. An amplification circuit controls the gain of the variable gain circuit by amplifying the difference between the output voltages of the peak detection circuit and average value detection/output amplitude setting circuit. The number of base-emitter junctions of transistors on a path in the peak detection circuit from input ports which receive output signals from the variable gain circuit to an output port which outputs a voltage to the amplification circuit is equal to the number of base-emitter junctions of transistors on a path in the average value detection/output amplitude setting circuit.

    摘要翻译： 在自动增益控制电路中，峰值检测电路检测并输出来自可变增益电路的输出信号的峰值电压。 平均值检测/输出振幅设定电路检测来自可变增益电路的输出信号的平均值电压，并输出计算出的电压。 放大电路通过放大峰值检测电路的输出电压和平均值检测/输出幅度设定电路之间的差来控制可变增益电路的增益。 从输入端口接收峰值检测电路中的路径上的晶体管的基极 - 发射极结数量，该输入端口从可变增益电路接收输出到放大电路的电压的输出端口等于基极 - 发射极 在平均值检测/输出幅度设置电路中的路径上的晶体管的结。

    AUTOMATIC GAIN CONTROL CIRCUIT
    10.
    发明申请
    AUTOMATIC GAIN CONTROL CIRCUIT 有权
    自动增益控制电路

    公开(公告)号：US20140097901A1

    公开(公告)日：2014-04-10

    申请号：US14114519

    申请日：2012-06-29

    申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

    发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

    IPC分类号： H03G3/30

    CPC分类号： H03G3/30 ,  H03G3/3084

    摘要： An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).

    摘要翻译： 自动增益控制电路（5a）包括检测来自可变增益放大器（3）的输出信号的峰值电压的峰值检测电路（10），检测平均值的平均值检测和输出幅度设定电路（11） 来自可变增益放大器（3）的输出信号的电压，并将可变增益放大器（3）的期望输出幅度的电压½加到平均电压上;以及高增益放大器（12），放大输出 峰值检测器电路（10）的电压和平均值检测和输出幅度设置电路（11）的输出电压，并且使用放大结果作为增益控制信号来控制可变增益放大器（3）的增益。 峰值检测器电路（10）包括晶体管（Q1，Q2，Q3），电流源（I1）和滤波器电路。 滤波电路包括电阻（Ra）和电容器（C1）的串联连接。