-
公开(公告)号：US06033231A
公开(公告)日：2000-03-07
申请号：US121812
申请日：1998-07-24
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10 , H01L29/417 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/41725 , H01L21/762 , H01L21/823412 , H01L29/1083 , H01L29/1087 , H01L29/66621 , H01L29/78 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).
摘要翻译： 梯形通道半导体器件（10）形成在基座（12）中。 与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。 基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。 互连结构（90）可以可选地与装置（10）的形成一起形成。 互连结构（90）具有多个导体（60,97），其可用于传输跨越设备（10）的电信号。
-
2.发明授权
公开(公告)号：US5920102A
公开(公告)日：1999-07-06
申请号：US867663
申请日：1997-05-30
CPC分类号： H01L27/0629
摘要： A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.
摘要翻译： 半导体器件（10）形成在覆盖外延层（12）和半导体衬底（11）的基座结构（16）中。 半导体器件（10）包括与外延层（12）形成PN结的掺杂区域（13）。 半导体器件（10）还包括具有露出掺杂区域（13）的一部分的开口（23）和露出外延层（12）的一部分的开口（24）的电介质层（22）。 开口（23,24）填充有导电材料（36,37）以提供触点（100,101）。 由于PN结的存在，触点（100,101）彼此电容耦合。
-
公开(公告)号：US5818098A
公开(公告)日：1998-10-06
申请号：US608864
申请日：1996-02-29
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234 , H01L29/10 , H01L29/417 , H01L29/423 , H01L23/58
CPC分类号： H01L29/41725 , H01L21/762 , H01L21/823412 , H01L29/1083 , H01L29/1087 , H01L29/66621 , H01L29/78 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).
摘要翻译： 梯形通道半导体器件（10）形成在基座（12）中。 与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。 基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。 互连结构（90）可以可选地与装置（10）的形成一起形成。 互连结构（90）具有多个导体（60,97），可用于传输电信号跨过装置（10）。
-
公开(公告)号：US5808362A
公开(公告)日：1998-09-15
申请号：US609251
申请日：1996-02-29
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/06 , H01L29/10 , H01L29/417 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/41775 , H01L21/8234 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/41783 , H01L29/66621 , H01L29/665 , H01L29/66537
摘要： A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).
摘要翻译： 梯形通道半导体器件（10）形成在基座（12）中。 与传统的装置结构相比，底座（12）形成在基板（11）上并改善了装置（10）的电气特性。 基座（12）具有由第一介电层（24）邻接以提供电隔离的侧面（13）。 互连结构（90）可以可选地与装置（10）的形成一起形成。 互连结构（90）具有多个导体（60,97），其可用于传输跨越设备（10）的电信号。
-
公开(公告)号：US5712501A
公开(公告)日：1998-01-27
申请号：US541536
申请日：1995-10-10
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7838 , H01L29/66537
摘要： A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.
摘要翻译： 分级沟道半导体器件（10）包括具有主表面（12）的衬底区域（11）。 源区域（13）和漏极区域（14）形成在衬底区域（11）中并且间隔开以形成沟道区域（16）。 掺杂区域（18）形成在沟道区域（16）中并且与源极区域（13），漏极区域（14）和主表面（12）间隔开。 掺杂区域（18）具有与沟道区域（16）相同的导电类型，但具有较高的掺杂剂浓度。 与现有技术的短沟道结构相比，器件（10）表现出增强的穿通电阻和改进的性能。
-
公开(公告)号：US6051456A
公开(公告)日：2000-04-18
申请号：US216990
申请日：1998-12-21
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/732 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).
摘要翻译： 半导体部件包括具有两个轻掺杂漏极区域（1300,1701），沟道区域（1702），位于沟道区域（1702）内的源极区域（1916））的不对称晶体管，位于沟道区域外部的漏极区域 1702），位于两个轻掺杂漏极区（1300,1701）中的至少一个上的电介质结构（1404），位于电介质结构（1404）的相对侧的两个栅电极（1902,1903），漏电极 （1901）和覆盖源区（1916）的源电极（1904）。 该半导体元件还包括另一晶体管，其具有位于介电结构（1405）之间形成基极（121）的基极（121）和集电极（123）之间的发射极（122）。
-
7.发明授权Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture 失效绝缘栅半导体器件具有在栅极结构的一部分下方的空腔和制造方法
公开(公告)号：US5612244A
公开(公告)日：1997-03-18
申请号：US408657
申请日：1995-03-21
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L29/42368 , H01L21/823807 , H01L21/823828 , H01L29/66659 , H01L21/28167
摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).
摘要翻译： 具有减小的栅极 - 漏极电容的绝缘栅场效应晶体管（10）和制造场效应晶体管（10）的方法。 掺杂剂阱（13）形成在半导体衬底（11）中。 栅极氧化物层（26）形成在掺杂剂阱（13）上，其中栅极氧化物层（26）和具有栅极接触部分（43）和栅极延伸部分（44）的栅极结构（41）。 栅极接触部分（43）允许与栅极结构（41）的电接触，而栅极延伸部分（44）用作有源栅极部分。 与栅极接触部分（43）相邻的栅极氧化物（26）的一部分被加厚以降低场效应晶体管（10）的栅极到漏极电容，从而增加绝缘栅极场效应晶体管（10）的带宽。
-
8.发明授权Semiconductor component including MOSFET with asymmetric gate electrode where the drain electrode over portions of the lightly doped diffusion region without a gate dielectric 有权半导体元件包括具有非对称栅极电极的MOSFET，其中漏电极在轻掺杂扩散区的部分上而没有栅极电介质
公开(公告)号：US6153905A
公开(公告)日：2000-11-28
申请号：US502694
申请日：2000-02-11
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L29/732 , H01L29/78 , H01L29/788
CPC分类号： H01L27/0623 , H01L21/8249
摘要： A semiconductor component includes an asymmetric transistor having two lightly doped drain regions (1300, 1701), a channel region (1702), a source region (1916) located within the channel region (1702), a drain region located outside the channel region (1702), a dielectric structure (1404) located over at least one of the two lightly doped drain regions (1300, 1701), two gate electrodes (1902, 1903) located at opposite sides of the dielectric structure (1404), a drain electrode (1901) overlying the drain region (1915), and a source electrode (1904) overlying the source region (1916). The semiconductor component also includes another transistor having an emitter electrode (122) located between a base electrode (121) and a collector electrode (123) where the base electrode (121) is formed over a dielectric structure (1405).
摘要翻译： 半导体部件包括具有两个轻掺杂漏极区域（1300,1701），沟道区域（1702），位于沟道区域（1702）内的源极区域（1916））的不对称晶体管，位于沟道区域外部的漏极区域 1702），位于两个轻掺杂漏极区（1300,1701）中的至少一个上的电介质结构（1404），位于电介质结构（1404）的相对侧的两个栅电极（1902,1903），漏电极 （1901）和覆盖源区（1916）的源电极（1904）。 该半导体元件还包括另一晶体管，其具有位于介电结构（1405）之间形成基极（121）的基极（121）和集电极（123）之间的发射极（122）。
-
9.发明授权Static random access memory cell having graded channel metal oxide semiconductor transistors and method of operation 失效具有分级沟道金属氧化物半导体晶体管的静态随机存取存储单元及其操作方法
公开(公告)号：US5886921A
公开(公告)日：1999-03-23
申请号：US762171
申请日：1996-12-09
IPC分类号： G11C11/41 , G11C11/412 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/41 , G11C11/412
摘要： An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).
摘要翻译： SRAM存储单元（40）使用GCMOS晶体管（42,44,56和58）来改善互补位线（60和62）的放电。 GCMOS晶体管（42,44,56和58）仅在晶体管的源极侧具有渐变沟道区域。 配置具有连接到互补位线（60和62）的漏极端子和具有连接到存储器单元输出的漏极端子的交叉耦合晶体管（42和44）的传输晶体管（56和58）改善了读取的定时 存储单元（40）的操作。
-
10.发明授权Differential amplifier having unilateral field effect transistors and process of fabricating 失效具有单向场效应晶体管的差分放大器及其制造工艺
公开(公告)号：US5811341A
公开(公告)日：1998-09-22
申请号：US762170
申请日：1996-12-09
申请人： Robert B. Davies , Andreas A. Wild
发明人： Robert B. Davies , Andreas A. Wild
IPC分类号： H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/4983 , H01L29/7835
摘要： A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect transistors (12, 14, 16) has an asymmetric channel doping profile. The performance of the differential amplifier (10) is significantly improved by properly orienting the three unilateral field effect transistors (12, 14, 16).
摘要翻译： 差分放大器（10）包括形成在半导体材料的共同阱（40）中的三个单边场效应晶体管（12,14,16）。 三个单侧场效应晶体管（12,14,16）中的每一个具有非对称沟道掺杂分布。 通过适当地定向三个单边场效应晶体管（12,14,16），差分放大器（10）的性能得到显着提高。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.019 秒)
