公开(公告)号：US5721167A

公开(公告)日：1998-02-24

申请号：US797142

申请日：1997-02-10

申请人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

发明人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

IPC分类号： H01L21/8244

CPC分类号： H01L27/11

摘要： A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.

摘要翻译： 形成具有具有多个SRAM单元的SRAM阵列的半导体器件（10）。 在形成访问和锁存晶体管时，使用两种不同的栅电极组合物来形成访问和锁存晶体管。 更具体地，在用于存取晶体管的栅电极（52）内的两个导电层（26和28）之间形成介电层（22），而在两个导电层（26和28）之间不形成介电层，用于 锁存晶体管。 该结构允许增加SRAM单元的β比，从而形成更稳定的SRAM单元，而不必在存储节点中的存取晶体管之间使用扩散电阻，或者必须在用于锁存晶体管的栅介质层之间形成差分厚度 和存取晶体管。

公开(公告)号：US6136678A

公开(公告)日：2000-10-24

申请号：US33422

申请日：1998-03-02

申请人： Olubunmi Adetutu ,  James D. Hayden ,  Chitra Subramanian ,  Archana Redkar ,  Anthony Mark Miscione ,  Mark G. Fernandes

发明人： Olubunmi Adetutu ,  James D. Hayden ,  Chitra Subramanian ,  Archana Redkar ,  Anthony Mark Miscione ,  Mark G. Fernandes

IPC分类号： C23C16/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28247 ,  C23C16/0227 ,  H01L21/28061 ,  H01L21/321 ,  H01L29/4933

摘要： A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.

摘要翻译： 用于处理诸如栅叠层的掺杂多晶硅层（14）的导电层的方法在预清洗之后提供脱气步骤以减少颗粒数量和缺陷率。 导电层设置在例如硅晶片的基板（10）上。 在真空下使衬底（10）和导电层经受升高的温度，从而释放某些物质。 然后将其上形成有导电层的衬底从腔室移除，并移动到沉积有第二导电层（20）的第二分离室。 通过切换室，释放的物质被大大地防止在导电层之间的界面处对颗粒计数的贡献。 或者，第二导电层形成在相同的室中，条件是在沉积第二导电层之前将释放的物质从室中除去。

公开(公告)号：US20070042546A1

公开(公告)日：2007-02-22

申请号：US11208670

申请日：2005-08-22

申请人： Jeffrey Thomas ,  Olubunmi Adetutu

发明人： Jeffrey Thomas ,  Olubunmi Adetutu

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.

摘要翻译： 半导体工艺和设备包括通过在半导体结构（10）上沉积氮化物层（20）来形成半导体器件，图案化和蚀刻氮化物层以形成图案化氮化物层（42,44），沉积多晶硅层 （62），用CMP工艺平坦化多晶硅层，以去除图案化的介电层（42,44）上方的多晶硅层（62）的任何部分，然后去除图案化的氮化物层（42,44），由此限定一个 或更多个可用作浮动栅极，晶体管栅极，位线或任何其它半导体器件特征的多晶硅特征（72,74,76）。

公开(公告)号：US20060273411A1

公开(公告)日：2006-12-07

申请号：US11146826

申请日：2005-06-07

申请人： Dina Triyoso ,  Olubunmi Adetutu ,  Hsing Tseng

发明人： Dina Triyoso ,  Olubunmi Adetutu ,  Hsing Tseng

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack may include depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers may include performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers may include depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer may include pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.

摘要翻译： 用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。 形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。 沉积介质堆叠可以包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。 沉积一个电介质层可以包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。 沉积多个子层可以包括沉积无氮的子层并沉积含氮的子层。 沉积无氮子层可以包括用HfCl 4脉冲发射ALD室，用惰性气体冲洗室，用H 2 O 2或D 2 并且用惰性气体清洗室。

公开(公告)号：US20060110892A1

公开(公告)日：2006-05-25

申请号：US10996319

申请日：2004-11-22

申请人： Marius Orlowski ,  Mark Foisy ,  Olubunmi Adetutu

发明人： Marius Orlowski ,  Mark Foisy ,  Olubunmi Adetutu

IPC分类号： H01L21/76

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878

摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.

摘要翻译： 半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。 在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。 衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。 可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。 可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。 因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

公开(公告)号：US20060094259A1

公开(公告)日：2006-05-04

申请号：US10980445

申请日：2004-11-03

申请人： David Gilmer ,  Olubunmi Adetutu ,  Hsing Tseng

发明人： David Gilmer ,  Olubunmi Adetutu ,  Hsing Tseng

IPC分类号： H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02318 ,  H01L21/02123 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/28185 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into the ambient while maintaining the ambient at the annealing temperature. This passivating ambient is then maintained at the annealing temperature for a specified duration. While maintaining the presence of the passivating gas in the ambient, the ambient temperature is then ramped down from the annealing temperature to a second temperature, which is preferably less than 100° C. The passivating gas is preferably hydrogen gas, deuterium gas, or a combination of the two. The annealing temperature is preferably greater than approximately 470° C.

摘要翻译： 半导体制造退火工艺包括在衬底上沉积高介电常数栅极电介质并退火栅极电介质。 对栅极电介质进行退火包括将栅极电介质暴露于惰性环境，并将惰性环境升温至退火温度。 然后将钝化气体引入环境中，同时保持环境处于退火温度。 然后将该钝化环境在退火温度下保持规定的持续时间。 在保持环境中的钝化气体的存在的同时，环境温度然后从退火温度下降到第二温度，其优选小于100℃。钝化气体优选为氢气，氘气或 两者的结合。 退火温度优选大于约470℃

公开(公告)号：US20050277294A1

公开(公告)日：2005-12-15

申请号：US10865268

申请日：2004-06-10

申请人： James Schaeffer ,  Darrell Roan ,  Dina Triyoso ,  Olubunmi Adetutu

发明人： James Schaeffer ,  Darrell Roan ,  Dina Triyoso ,  Olubunmi Adetutu

IPC分类号： C23C16/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/44

CPC分类号： H01L21/02181 ,  C23C16/0272 ,  H01L21/3141 ,  H01L21/31645

摘要： A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.

摘要翻译： 一种用于处理半导体表面以形成含金属层的方法包括提供具有暴露表面的半导体衬底。 半导体衬底的暴露表面通过形成覆盖半导体衬底但不完全覆盖半导体衬底的暴露表面的一种或多种金属来处理。 一种或多种金属增强成核以用于随后的材料生长。 在已经处理的半导体衬底的暴露表面上形成含金属层。 半导体衬底的暴露表面的处理有助于含金属层的聚结。 在一个实施方案中，可以通过旋涂，原子层沉积（ALD），物理层沉积（PVD），电镀或无电镀来进行暴露表面的处理以增强成核。 用于处理暴露表面的一种或多种金属可以包括任何稀土或过渡金属，例如铪，镧等。

公开(公告)号：US06376349B1

公开(公告)日：2002-04-23

申请号：US09487472

申请日：2000-01-19

申请人： Philip J. Tobin ,  Olubunmi Adetutu ,  Bikas Maiti

发明人： Philip J. Tobin ,  Olubunmi Adetutu ,  Bikas Maiti

IPC分类号： H01L213205

CPC分类号： H01L29/4958 ,  H01L21/28079

摘要： Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.

摘要翻译： 可以形成具有金属层的半导体器件和导电结构。 在一个实施例中，半导体器件包括非晶金属层（22）和结晶金属层（42）。 无定形金属层（22）有助于降低污染物穿过非晶金属层（22）的可能性。 可以在非晶金属层（22）上形成更导电的晶体金属层（42），以帮助保持电阻率相对较低。 当形成导电结构时，含金属的气体和清除气体在至少一个时间点内同时流动。 导电结构可以是栅电极的一部分。

公开(公告)号：US5888588A

公开(公告)日：1999-03-30

申请号：US828638

申请日：1997-03-31

申请人： Rajan Nagabushnam ,  Olubunmi Adetutu ,  Yeong-Jyh Tom Lii

发明人： Rajan Nagabushnam ,  Olubunmi Adetutu ,  Yeong-Jyh Tom Lii

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L29/49 ,  C23C16/00 ,  H01L21/285

CPC分类号： C23C16/34 ,  H01L21/28061 ,  H01L29/4941

摘要： A semiconductor device (10) includes a gate electrode (61) having a silicon/tungsten nitride/tungsten silicon nitride/tungsten silicide composition. The tungsten nitride film (21) and tungsten suicide film (23) are formed using chemical vapor deposition (CVD). The tungsten nitride film is formed using a tungsten halide and N.sub.2 R.sup.1 R.sup.2, where each of R.sup.1 and R.sup.2 is hydrogen, an alkyl group, an alkenyl group, or an alkynyl group. The tungsten nitride film (21) is an etch stop when patterning the tungsten silicide film (23). The CVD tungsten nitride film (21) helps to improve gate dielectric integrity and reduces interface traps when compared to a sputtered tungsten nitride film (21). Also, N.sub.2 R.sup.1 R.sup.2 can be used to remove halogens that are adsorbed onto walls of a reaction chamber than is cleaned between depositions of substrates.

摘要翻译： 半导体器件（10）包括具有硅/氮化钨/氮化钨/硅化钨组合物的栅电极（61）。 使用化学气相沉积（CVD）形成氮化钨膜（21）和硅化钨膜（23）。 氮化钨膜使用卤化钨和N 2 R 1 R 2形成，其中R 1和R 2各自为氢，烷基，烯基或炔基。 当图案化硅化钨膜（23）时，氮化钨膜（21）是蚀刻停止层。 与溅射的氮化钨膜（21）相比，CVD氮化钨膜（21）有助于提高栅极电介质完整性并减少界面陷阱。 此外，N2R1R2可用于除去吸附到反应室壁上的卤素，而不是在底物沉积之间清洗的卤素。

公开(公告)号：US20070166973A1

公开(公告)日：2007-07-19

申请号：US11331786

申请日：2006-01-13

申请人： Shahid Rauf ,  Olubunmi Adetutu ,  Eric Luckowski ,  Peter Ventzek

发明人： Shahid Rauf ,  Olubunmi Adetutu ,  Eric Luckowski ,  Peter Ventzek

IPC分类号： H01L21/467

CPC分类号： H01L21/02071 ,  H01L21/28088 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

摘要翻译： 金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。 去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82） ）。 接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95） （80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。