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    Process for forming a semiconductor device and a static-random-access memory cell
    1.
    发明授权
    Process for forming a semiconductor device and a static-random-access memory cell 失效
    用于形成半导体器件和静态随机存取存储器单元的工艺

    公开(公告)号：US5721167A

    公开(公告)日：1998-02-24

    申请号：US797142

    申请日：1997-02-10

    申请人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

    发明人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/11

    摘要： A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.

    摘要翻译： 形成具有具有多个SRAM单元的SRAM阵列的半导体器件（10）。 在形成访问和锁存晶体管时，使用两种不同的栅电极组合物来形成访问和锁存晶体管。 更具体地，在用于存取晶体管的栅电极（52）内的两个导电层（26和28）之间形成介电层（22），而在两个导电层（26和28）之间不形成介电层，用于 锁存晶体管。 该结构允许增加SRAM单元的β比，从而形成更稳定的SRAM单元，而不必在存储节点中的存取晶体管之间使用扩散电阻，或者必须在用于锁存晶体管的栅介质层之间形成差分厚度 和存取晶体管。

    Method of processing a conductive layer and forming a semiconductor device
    2.
    发明授权
    Method of processing a conductive layer and forming a semiconductor device 失效
    处理导电层并形成半导体器件的方法

    公开(公告)号：US6136678A

    公开(公告)日：2000-10-24

    申请号：US33422

    申请日：1998-03-02

    申请人： Olubunmi Adetutu ,  James D. Hayden ,  Chitra Subramanian ,  Archana Redkar ,  Anthony Mark Miscione ,  Mark G. Fernandes

    发明人： Olubunmi Adetutu ,  James D. Hayden ,  Chitra Subramanian ,  Archana Redkar ,  Anthony Mark Miscione ,  Mark G. Fernandes

    IPC分类号： C23C16/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28247 ,  C23C16/0227 ,  H01L21/28061 ,  H01L21/321 ,  H01L29/4933

    摘要： A method for processing a conductive layer, such as a doped polysilicon layer (14) of a gate stack, provides a degas step after precleaning to reduce particle count and defectivity. The conductive layer is provided on a substrate (10), e.g., a silicon wafer. The substrate (10) and conductive layer are subjected to an elevated temperature, under a vacuum, whereby certain species are liberated. The substrate having the conductive layer formed thereon is then removed from the chamber, and moved to a second, separate chamber, in which a second conductive layer (20) is deposited. By switching chambers, the liberated species are largely prevented from contributing to particle count at the interface between the conductive layers. Alternatively, the second conductive layer is formed in the same chamber, provided that the liberated species are removed from the chamber prior to deposition of the second conductive layer.

    摘要翻译： 用于处理诸如栅叠层的掺杂多晶硅层（14）的导电层的方法在预清洗之后提供脱气步骤以减少颗粒数量和缺陷率。 导电层设置在例如硅晶片的基板（10）上。 在真空下使衬底（10）和导电层经受升高的温度，从而释放某些物质。 然后将其上形成有导电层的衬底从腔室移除，并移动到沉积有第二导电层（20）的第二分离室。 通过切换室，释放的物质被大大地防止在导电层之间的界面处对颗粒计数的贡献。 或者，第二导电层形成在相同的室中，条件是在沉积第二导电层之前将释放的物质从室中除去。

    Method for forming a dual transistor structure
    4.
    发明授权
    Method for forming a dual transistor structure 失效
    形成双晶体管结构的方法

    公开(公告)号：US5413948A

    公开(公告)日：1995-05-09

    申请号：US209763

    申请日：1994-03-14

    申请人： James R. Pfiester ,  James D. Hayden

    发明人： James R. Pfiester ,  James D. Hayden

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/78696 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/42376 ,  H01L29/78642 ,  Y10S257/903

    摘要： A transistor structure (10) has a substrate (12). A first transistor is formed within the substrate (12) having a source region (38), a drain region (30), and a gate electrode formed by a first spacer (26a). A second transistor is formed within the substrate (12) by the source region (38), a drain region (28), and a gate electrode formed by a second spacer (26a). A third transistor is formed overlying the first transistor. The third transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the first spacer (26a). A fourth transistor is formed overlying the second transistor. The fourth transistor has a source region (34a), a drain region (34c), a channel region (34b), and a gate electrode formed by the second spacer (26a). The first, second, third, and fourth transistors may be interconnected to form a portion of a compact static random access memory (SRAM) cell.

    摘要翻译： 晶体管结构（10）具有基板（12）。 第一晶体管形成在具有源极区（38），漏极区（30）和由第一间隔物（26a）形成的栅电极的衬底（12）内。 第二晶体管由源极区（38），漏极区（28）和由第二间隔物（26a）形成的栅极形成在衬底（12）内。 第三晶体管形成在第一晶体管的上方。 第三晶体管具有源极区（34a），漏极区（34c），沟道区（34b）和由第一间隔物（26a）形成的栅电极。 第四晶体管形成在第二晶体管的上方。 第四晶体管具有源极区（34a），漏极区（34c），沟道区（34b）和由第二间隔物（26a）形成的栅电极。 第一，第二，第三和第四晶体管可以互连以形成小型静态随机存取存储器（SRAM）单元的一部分。

    Vertically formed semiconductor random access memory device
    5.
    发明授权
    Vertically formed semiconductor random access memory device 失效
    垂直形成的半导体随机存取存储器件

    公开(公告)号：US5398200A

    公开(公告)日：1995-03-14

    申请号：US183086

    申请日：1994-01-18

    申请人： Carlos A. Mazure ,  Jon T. Fitch ,  James D. Hayden ,  Keith E. Witek

    发明人： Carlos A. Mazure ,  Jon T. Fitch ,  James D. Hayden ,  Keith E. Witek

    IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L27/01

    CPC分类号： H01L21/76897 ,  H01L27/1108 ,  H01L27/1112 ,  H01L29/66666 ,  H01L29/7827 ,  H01L27/0688 ,  Y10S257/904

    摘要： A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

    摘要翻译： 形成具有基板（12）的半导体存储器件。 在衬底（12）内形成扩散（14）。 形成第一垂直晶体管堆叠（122）。 形成第二垂直晶体管堆叠（124）。 第一垂直晶体管堆叠（122）具有位于晶体管（104）下面的晶体管（100）。 第二垂直晶体管堆叠（124）具有位于晶体管（106）下方的晶体管（102）。 晶体管（100和104）串联连接，晶体管（102和106）串联连接。 在优选形式中，晶体管（100和102）电连接作为用于半导体存储器件的锁存晶体管，并且晶体管（106和104）作为传输晶体管连接。 两个垂直堆叠（126和128）形成用于半导体存储器件的电互连（118和120）和电阻器件（134和138）。

    Process for forming a static-random-access memory cell
    6.
    发明授权
    Process for forming a static-random-access memory cell 失效
    形成静态随机存取存储单元的过程

    公开(公告)号：US5393689A

    公开(公告)日：1995-02-28

    申请号：US209170

    申请日：1994-02-28

    申请人： James R. Pfiester ,  James D. Hayden

    发明人： James R. Pfiester ,  James D. Hayden

    IPC分类号： H01L27/11 ,  H01L21/8244 ,  H01L21/70

    CPC分类号： H01L27/11 ,  Y10S257/903

    摘要： An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

    摘要翻译： 形成SRAM单元，使得与与锁存晶体管相邻的锁存通道停止区域相比，与通过晶体管相邻的通过通道停止区域具有较高的掺杂浓度。 在一个实施例中，通道通道停止区域是使用两个通道停止掺杂步骤形成的，而锁存通道停止区域仅在一个通道停止掺杂步骤期间形成。 掺杂步骤可以在形成场隔离之前或之后进行。 与锁存通道停止区域相比，较高的掺杂浓度使来自通道 - 停止区域的掺杂剂从场隔离的边缘横向延伸。 该过程可以适用于几乎任何类型的现场隔离过程。

    Method of making a six transistor static random access memory cell
    7.
    发明授权
    Method of making a six transistor static random access memory cell 失效
    制造六晶体管静态随机存取存储单元的方法

    公开(公告)号：US5330929A

    公开(公告)日：1994-07-19

    申请号：US955785

    申请日：1992-10-05

    申请人： James R. Pfiester ,  James D. Hayden

    发明人： James R. Pfiester ,  James D. Hayden

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S148/059

    摘要： The present invention includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise an active region and a first layer. The active region including a first segment, a second segment, and a third segment, wherein 1) the first segment has an adjacent end and a distal end; 2) the second segment is generally parallel to the first segment, and has an adjacent end and a distal end; and 3) the third segment is generally perpendicular to the first direction, wherein the adjacent end of the first segment lies near one end of the third segment, wherein the adjacent end of the second segment lies near the other end of the third segment. The first layer has the a shape similar to the active region except that the first layer does not lie over the first and second segments near the distal ends. The present invention also includes a static random access memory cell and a method of forming the memory cell, wherein the memory cell may comprise shared gate electrodes that overlap one another without electrically contacting each other.

    摘要翻译： 本发明包括静态随机存取存储器单元和形成存储单元的方法，其中存储单元可以包括有源区和第一层。 所述活动区域包括第一段，第二段和第三段，其中1）所述第一段具有相邻端和远端; 2）第二段通常平行于第一段，并具有相邻端和远端; 以及3）所述第三段通常垂直于所述第一方向，其中所述第一段的相邻端靠近所述第三段的一端，其中所述第二段的相邻端靠近所述第三段的另一端。 第一层具有类似于活性区域的形状，除了第一层不位于远端附近的第一和第二区段之外。 本发明还包括静态随机存取存储器单元和形成存储单元的方法，其中存储单元可以包括彼此重叠而不彼此电接触的共享栅电极。

    Transistor useful for further vertical integration and method of formation
    8.
    发明授权
    Transistor useful for further vertical integration and method of formation 失效
    晶体管有助于进一步垂直整合和形成方法

    公开(公告)号：US5252849A

    公开(公告)日：1993-10-12

    申请号：US844037

    申请日：1992-03-02

    申请人： Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek ,  James D. Hayden

    发明人： Jon T. Fitch ,  Carlos A. Mazure ,  Keith E. Witek ,  James D. Hayden

    IPC分类号： H01L21/8249 ,  H01L21/331 ,  H01L21/336 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

    CPC分类号： H01L29/66287 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/66666 ,  H01L29/6675 ,  H01L29/732 ,  H01L29/7827

    摘要： A transistor is formed as either a bipolar transistor (10) or an MOS transistor (11). Each transistor (10 or 11) has a substrate (12). Bipolar transistor (10) has a first current electrode (26) underlying a control electrode (28), and a second current electrode (32) overlying the control electrode (28). MOS transistor (11) has a first current electrode (54) underlying a channel region (56), and a source lightly doped region (58) and a source heavily doped region (60) overlying the channel region (56). A control electrode conductive layer (40) is laterally adjacent a sidewall dielectric layer (48), and sidewall dielectric layer (48) is laterally adjacent channel region (56). Conductive layer (40) functions as a gate electrode for transistor (11). Each of the transistors (10 and 11) is vertically integrated such as in a vertically integrated BiMOS circuit. Transistors (10 and 11) can be electrically isolated by isolation ( 64 and 66).

    摘要翻译： 晶体管形成为双极晶体管（10）或MOS晶体管（11）。 每个晶体管（10或11）具有衬底（12）。 双极晶体管（10）具有位于控制电极（28）下方的第一电流电极（26）和覆盖控制电极（28）的第二电流电极（32）。 MOS晶体管（11）具有位于沟道区（56）下面的第一电流电极（54）和覆盖沟道区（56）的源极轻掺杂区（58）和源极重掺杂区（60）。 控制电极导电层（40）横向邻近侧壁电介质层（48），侧壁电介质层（48）横向邻近沟道区域（56）。 导电层（40）用作晶体管（11）的栅电极。 每个晶体管（10和11）是垂直集成的，例如在垂直集成的BiMOS电路中。 晶体管（10和11）可通过隔离电隔离（64和66）。

    High-performance thin-film transistor and SRAM memory cell
    9.
    发明授权
    High-performance thin-film transistor and SRAM memory cell 失效
    高性能薄膜晶体管和SRAM存储单元

    公开(公告)号：US5567958A

    公开(公告)日：1996-10-22

    申请号：US452944

    申请日：1995-05-31

    申请人： Marius Orlowski ,  James D. Hayden ,  Bich-Yen Nguyen

    发明人： Marius Orlowski ,  James D. Hayden ,  Bich-Yen Nguyen

    IPC分类号： H01L21/336 ,  H01L27/11 ,  H01L29/786 ,  H01L29/78

    CPC分类号： H01L27/1108 ,  H01L29/66757 ,  H01L29/78696 ,  Y10S257/903

    摘要： A thin-film transistor and SRAM memory cell include thin-film source and drain regions (12, 14) separated by an opening (22) and overlying and insulating layer (11). A thin-film channel layer (16) overlies the thin-film source and drain regions (12, 14) and a portion of the insulating layer (11) exposed by the opening (22). A thin-film gate electrode (20) is positioned in the opening (22) and defines a thin-film channel region (24) in the thin-film channel layer (16). The thin-film gate electrode (20) is separated from the thin-film channel region (24) by a gate dielectric layer (18). The thin-film channel region (24) extends along vertical wall surfaces (26, 28) of the thin-film source and drain regions (12, 14) providing an extended channel length for the thin-film transistor.

    摘要翻译： 薄膜晶体管和SRAM存储单元包括由开口（22）和上覆绝缘层（11）分开的薄膜源区和漏区（12,14）。 薄膜通道层（16）覆盖薄膜源区和漏区（12,14），绝缘层（11）的一部分由开口（22）露出。 薄膜栅电极（20）位于开口（22）中并且在薄膜通道层（16）中限定薄膜通道区（24）。 薄膜栅电极（20）通过栅介质层（18）与薄膜沟道区（24）分离。 薄膜通道区域（24）沿薄膜源极和漏极区域（12,14）的垂直壁表面（26,28）延伸，为薄膜晶体管提供延长的沟道长度。