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1.发明授权Precision, high speed delay system for providing delayed clock edges with new delay values every clock period 失效精确的高速延迟系统，用于在每个时钟周期提供延迟时钟边沿，并具有新的延迟值公开(公告)号：US06373312B1
公开(公告)日：2002-04-16
申请号：US09672030
申请日：2000-09-29
申请人： Robert K. Barnes , Randy L. Bailey
发明人： Robert K. Barnes , Randy L. Bailey
IPC分类号： H03H1126
CPC分类号： H03K5/1252 , H03K5/133 , H03K5/1565
摘要： A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.
摘要翻译： 精确延迟系统允许时钟沿在每个时钟周期T被延迟新的延迟值。每个时钟周期对内部延迟元件进行重新编程，重新编程瞬变被时钟独立的消隐电路抑制。 该系统允许使用具有时钟周期的一半（T / 2）的最大延迟的延迟元件，以全周期循环重新编程连续跨越整个时钟周期T延迟范围。
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公开(公告)号：US08634503B2
公开(公告)日：2014-01-21
申请号：US13076640
申请日：2011-03-31
申请人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
发明人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
IPC分类号： H04L27/00
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/081
摘要： A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.
摘要翻译： 时钟数据恢复系统和方法促进对输入数据信号中的大相位变化的快速调整。 该系统可以包括相位对准电路，时钟发生器电路，时间 - 数字转换器电路和采样电路。 相位对准电路使用输入数据信号和反馈时钟信号来产生输出时钟信号。 时钟发生器电路使用输出时钟信号来产生不同相位或极性的基相时钟信号。 时间 - 数字转换器电路使用基本相位时钟信号和输入数据信号来产生反馈时钟信号。 时基数字转换器电路将反馈时钟信号与基本相位时钟信号相比较，其基准相位时钟信号与输入的数据信号与其它基本相位时钟信号相比更紧密地对准。 采样电路使用一个或多个基本相位时钟信号重新计时或恢复数据信号。
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公开(公告)号：US20120250811A1
公开(公告)日：2012-10-04
申请号：US13076640
申请日：2011-03-31
申请人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
发明人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/081
摘要： A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.
摘要翻译： 时钟数据恢复系统和方法促进对输入数据信号中的大相位变化的快速调整。 该系统可以包括相位对准电路，时钟发生器电路，时间 - 数字转换器电路和采样电路。 相位对准电路使用输入数据信号和反馈时钟信号来产生输出时钟信号。 时钟发生器电路使用输出时钟信号来产生不同相位或极性的基相时钟信号。 时间 - 数字转换器电路使用基本相位时钟信号和输入数据信号来产生反馈时钟信号。 时基数字转换器电路将反馈时钟信号与基本相位时钟信号相比较，其基准相位时钟信号与输入的数据信号与其它基本相位时钟信号相比更紧密地对准。 采样电路使用一个或多个基本相位时钟信号重新计时或恢复数据信号。
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4.发明授权Clock enable circuit for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality 有权时钟使能电路，用于包含无毛刺启用/禁用功能的高速可编程延迟线公开(公告)号：US06348828B1
公开(公告)日：2002-02-19
申请号：US09672903
申请日：2000-09-29
申请人： Robert K. Barnes
发明人： Robert K. Barnes
IPC分类号： G06F104
CPC分类号： H03K5/1252 , H03K5/13
摘要： A clock qualification circuit used to selectively enable a clock edge to transfer new delay data from a first-in-first-out (FIFO) circuit in a precision delay line circuit. The circuit qualifies the clock without generating undesirable pulses (glitches) and causing false loading of new delay data in a timing on the fly delay line implementation.
摘要翻译： 时钟鉴定电路，用于选择性地使时钟沿从精密延迟线电路中的先进先出（FIFO）电路传输新的延迟数据。 该电路对时钟进行限定，而不会产生不期望的脉冲（毛刺），并在飞行延迟线实现的定时中引起新的延迟数据的错误加载。
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公开(公告)号：US5315456A
公开(公告)日：1994-05-24
申请号：US869603
申请日：1992-04-16
CPC分类号： G11B20/1258 , G11B19/02 , G11B27/10 , G11B27/3027 , G11B2020/1282 , G11B2220/20
摘要： A disk drive has a disk format that includes servo fields and interspersed data fields. The disk drive includes a timing generator for generating timing signals to synchronize and control operation of read/write and servo positioning circuits. The disk drive also includes a writable program store that stores a plurality of timing signal commands for generating timing signals in conformance with the format of a disk. A processor loads the writable program store with the timing signal commands and the processor further enables readout of those commands from the writable program store. An execution register receives the timing signal commands and generates timing signals in response, the timing signals controlling synchronization and operation of the read/write circuits. As the writable program store is reprogrammable, at will, substantial flexibility is achieved in the creation of such timing signals.
摘要翻译： 磁盘驱动器具有包括伺服字段和散布数据字段的磁盘格式。 盘驱动器包括定时发生器，用于产生定时信号以同步和控制读/写和伺服定位电路的操作。 磁盘驱动器还包括可写程序存储器，其存储用于根据磁盘的格式产生定时信号的多个定时信号命令。 处理器使用定时信号命令加载可写程序存储器，并且处理器还允许从可写程序存储器读出这些命令。 执行寄存器接收定时信号命令并产生响应中的定时信号，定时信号控制读/写电路的同步和操作。 由于可写程序存储器是可重新编程的，所以在创建这样的定时信号时，可以随意地获得实质的灵活性。
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6.发明授权Programmable start-of-sector pulse generator for a disk drive using embedded servo bursts and split data fields 失效使用嵌入式伺服突发和分割数据字段的磁盘驱动器的可编程起始扇区脉冲发生器
公开(公告)号：US5276564A
公开(公告)日：1994-01-04
申请号：US869602
申请日：1992-04-16
CPC分类号： G11B20/1258 , G11B19/02 , G11B21/085 , G11B27/3027 , G11B2020/1282
摘要： A disk drive system employs uniform size data blocks, with each disk having a sectorized track format and each sector of a track including at least one servo burst. Data blocks exhibit a constant data density across a plurality of disk tracks of differing radii. The system comprises read/write apparatus for accessing both servo signals and data signals in each disk sector. A servo system is responsive to servo signals fed from the read/write apparatus to generate a synchronizing signal. A data sector pulse generation circuit is responsive to the synchronizing signal to generate and pass to the read/write apparatus, a data sector pulse for each block of data commencing in a sector. That data sector pulse enables operation of the read/write apparatus upon the data block. A control circuit enables the delay of generation of a next data sector pulse when any block of data is split by a servo burst. The delay period is the duration of the servo burst and the portion of the data block that follows the servo burst.
摘要翻译： 磁盘驱动器系统采用均匀尺寸的数据块，每个磁盘具有扇区化的磁道格式，并且磁道的每个扇区包括至少一个伺服脉冲串。 数据块在不同半径的多个磁盘轨道上呈现恒定的数据密度。 该系统包括用于访问每个磁盘扇区中的伺服信号和数据信号的读/写装置。 伺服系统响应于从读/写装置馈送的伺服信号以产生同步信号。 数据扇区脉冲发生电路响应于同步信号以产生并传递给读/写设备，用于从扇区开始的每个数据块的数据扇区脉冲。 该数据扇区脉冲允许读/写设备在数据块上的操作。 当任何数据块被伺服脉冲分割时，控制电路能够延迟产生下一个数据扇区脉冲。 延迟周期是伺服脉冲串的持续时间和跟随伺服脉冲串的数据块的部分。
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公开(公告)号：US08698567B2
公开(公告)日：2014-04-15
申请号：US13437662
申请日：2012-04-02
申请人： Robert Thelen , Michael Farmer , Robert K. Barnes
发明人： Robert Thelen , Michael Farmer , Robert K. Barnes
摘要： In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.
摘要翻译： 在锁相环（PLL）校准系统和方法中，PLL输入参考时钟进行相位调制，测量得到的PLL输出调制，PLL校准信号，如PLL比例路径调整信号和PLL积分路径 调整信号，源自测量的PLL输出调制。
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公开(公告)号：US20130257497A1
公开(公告)日：2013-10-03
申请号：US13437662
申请日：2012-04-02
申请人： Robert Thelen , Michael Farmer , Robert K. Barnes
发明人： Robert Thelen , Michael Farmer , Robert K. Barnes
IPC分类号： H03L7/08
摘要： In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.
摘要翻译： 在锁相环（PLL）校准系统和方法中，PLL输入参考时钟进行相位调制，测量得到的PLL输出调制，PLL校准信号，如PLL比例路径调整信号和PLL积分路径 调整信号，源自测量的PLL输出调制。
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