公开(公告)号：US06665855B2

公开(公告)日：2003-12-16

申请号：US10016731

申请日：2001-12-11

申请人： Robert Payne ,  Mark Bapst ,  Timothy Pontius

发明人： Robert Payne ,  Mark Bapst ,  Timothy Pontius

IPC分类号： G06F1750

CPC分类号： G06F17/50 ,  G06F17/5022 ,  G06F17/5045

摘要： A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

摘要翻译： 快速硅加工布置显着减少了从初始设计到市场引入的时间。 与本发明的一个实施例一致，快速硅处理装置使用可解码和可扩展的参考芯片开发平台，其包括诸如电子可重构门阵列的可编程设备和用于与外部设备进行通信的非平台总线。 可以通过一个或多个功能块宏来取消选择交互活动来解除参考芯片开发平台的配置。 外部设备可以与参考芯片开发平台一起使用，以测试参考芯片开发平台内​​可编程设备中的功能块宏的合成子集的硬件表示，如由平台外总线所扩展的。 该方法大大减少了从初始设计到市场引入的开发时间。

公开(公告)号：US06347395B1

公开(公告)日：2002-02-12

申请号：US09215942

申请日：1998-12-18

申请人： Robert Payne ,  Mark Bapst ,  Timothy Pontius

发明人： Robert Payne ,  Mark Bapst ,  Timothy Pontius

IPC分类号： G06F1750

CPC分类号： G06F17/50 ,  G06F17/5022 ,  G06F17/5045

摘要： A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

摘要翻译： 快速硅加工布置显着减少了从初始设计到市场引入的时间。 与本发明的一个实施例一致，快速硅处理装置使用可解码和可扩展的参考芯片开发平台，其包括诸如电子可重构门阵列的可编程设备和用于与外部设备进行通信的非平台总线。 可以通过一个或多个功能块宏来取消选择交互活动来解除参考芯片开发平台的配置。 外部设备可以与参考芯片开发平台一起使用，以测试参考芯片开发平台内​​可编程器件中的功能块宏的合成的硬件表示，如由平台外总线所扩展。 该方法大大减少了从初始设计到市场引入的开发时间。

公开(公告)号：US06839862B2

公开(公告)日：2005-01-04

申请号：US09871159

申请日：2001-05-31

申请人： David R. Evoy ,  Timothy Pontius ,  Gregory E. Ehmann

发明人： David R. Evoy ,  Timothy Pontius ,  Gregory E. Ehmann

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L25/02 ,  H04L25/14 ,  G06F1/04 ,  G06F1/12 ,  G04L7/00

CPC分类号： H04L7/0008 ,  H04L25/14

摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

摘要翻译： 在一个示例实施例中，高速并行数据通信方法通过包括多个并行数据携带线路和时钟路径的通信信道将数字数据从第一模块并行传送到第二模块。 并行总线布置成多个组，每个组包括多个数据传送线和适于承载时钟信号的时钟路径，用于将从第一模块承载的数字数据同步到第二模块。 使用并行总线的线路并行传送数据组，并且在第二模块处，并且对于每个组，经由该组的时钟信号同步地收集传送的数字数据。 在第二个模块中，对每个组收集的数据进行对齐。 通过将每个组具有自己的时钟域的组中的总线分组，通过在每个时钟域组内，然后在组之间首先处理数据和偏移来容忍和克服时钟域组之间的偏斜。

公开(公告)号：US06467010B1

公开(公告)日：2002-10-15

申请号：US09513009

申请日：2000-02-25

申请人： Timothy Pontius ,  Mark Johnson

发明人： Timothy Pontius ,  Mark Johnson

IPC分类号： G06F1340

CPC分类号： G06F13/4059

摘要： A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

摘要翻译： 一种方法和装置在两个总线之间传递数据，而不需要传统的桥接口协议。 根据本发明的一个方法实施例，使用在外部总线和第一总线之间的双向缓冲器布置，在参考芯片上的第一总线和外部总线之间传递数据。 该方法包括在外部总线和第一总线之间耦合双向缓冲器布置，确定哪个总线是起始总线，并且响应于该确定，控制双向缓冲器布置以异步地复制数据通过两个 从起始总线到另一总线的缓冲器布置，其中响应于其在缓冲器布置处的存在而自动地传送数据，而没有任何时钟周期延迟。 示例应用涉及与用于快速硅处理芯片的总线的接口。

公开(公告)号：US06636166B2

公开(公告)日：2003-10-21

申请号：US09871197

申请日：2001-05-31

申请人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

发明人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

IPC分类号： H03M700

CPC分类号： H04L25/4908 ,  H04L25/14

摘要： In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

公开(公告)号：US6154803A

公开(公告)日：2000-11-28

申请号：US216291

申请日：1998-12-18

申请人： Timothy Pontius ,  Mark Johnson

发明人： Timothy Pontius ,  Mark Johnson

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4059

摘要： A method and arrangement passes data between two busses without needing conventional bridge-interface protocols. Consistent with one method embodiment of the present invention, data is passed between a first bus on a reference chip and an external bus using a two-way buffer arrangement between the external bus and the first bus. The method includes coupling a two-way buffer arrangement between the external bus and the first bus, determining which of the busses is the initiating bus, and in response to this determination, controlling the two-way buffer arrangement to asynchronously copy data through the two-way buffer arrangement from the initiating bus to the other bus, wherein data is passed automatically in response to its presence at the buffer arrangement without any clock cycle delays. An example application is directed to interfacing with a bus used for a rapid silicon processing chip.

公开(公告)号：US08078948B2

公开(公告)日：2011-12-13

申请号：US11576345

申请日：2005-09-28

申请人： Timothy Pontius ,  Jens Roever

发明人： Timothy Pontius ,  Jens Roever

IPC分类号： G06F11/00

CPC分类号： G06F13/4226

摘要： A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example embodiment, a data communication arrangement includes a plurality of target modules, and a first XOR tree arranged to provide a first data integrity-indicating signal and to respond to a respective second data integrity-indicating signal from each of the target modules. A second XOR tree is arranged to provide a first data bus and to respond to a respective second data bus from each of the target modules. Also, a controller module is used to determine availability of data on the first data bus in response to the first data integrity-indicating signal.

摘要翻译： 数据通信布置允许使用两相协议在控制器模块和多个目标模块之间进行有效的数据传输。 控制器模块和目标模块可以分别驻留在不同的时钟域中。 与一个示例性实施例一致，数据通信装置包括多个目标模块和第一异或树，其被布置为提供第一数据完整性指示信号并且响应来自每个目标模块的各自的第二数据完整性指示信号 。 第二异或树被布置成提供第一数据总线并且响应来自每个目标模块的相应的第二数据总线。 此外，控制器模块用于响应于第一数据完整性指示信号来确定第一数据总线上的数据的可用性。

公开(公告)号：US07187741B2

公开(公告)日：2007-03-06

申请号：US09999007

申请日：2001-10-31

申请人： Timothy Pontius ,  Robert L. Payne ,  David R. Evoy

发明人： Timothy Pontius ,  Robert L. Payne ,  David R. Evoy

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L7/02 ,  G06F5/10 ,  G06F2205/102 ,  H04L7/0008 ,  H04L7/005

摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

摘要翻译： 提供了将数据从源时钟域传递到非同步接收时钟域的方法和装置。 位于源时钟域的第一处理电路将写入地址信息与数据相连接，并且时钟发生器在与源时钟同步的源时钟域中生成发送时钟信号。 第一处理电路将时钟信号和具有链接的写入地址信息的数据发送到接收时钟域中的第二处理电路。 在接收时钟域中，第二处理电路将数据写入指定对应于链接的写入地址信息的存储元件的地址。 第二处理电路响应于来自源时钟域的写入使能信号将数据与伴随的发送时钟信号同步地存储到存储元件中，并且从存储元件读出与接收域时钟同步的数据。

公开(公告)号：US07085950B2

公开(公告)日：2006-08-01

申请号：US09966297

申请日：2001-09-28

申请人： Gregory E. Ehmann ,  D. C. Sessions ,  Timothy Pontius

发明人： Gregory E. Ehmann ,  D. C. Sessions ,  Timothy Pontius

IPC分类号： G06F13/14 ,  G06F1/24

CPC分类号： H04L7/0008 ,  H04L25/14

摘要： A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

公开(公告)号：US06996106B2

公开(公告)日：2006-02-07

申请号：US09997609

申请日：2001-11-29

申请人： Robert L. Payne ,  David R. Evoy ,  Timothy Pontius ,  George Ellis Spatz

发明人： Robert L. Payne ,  David R. Evoy ,  Timothy Pontius ,  George Ellis Spatz

IPC分类号： H04L12/28

CPC分类号： G06F13/126

摘要： A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.