公开(公告)号：US07187741B2

公开(公告)日：2007-03-06

申请号：US09999007

申请日：2001-10-31

申请人： Timothy Pontius ,  Robert L. Payne ,  David R. Evoy

发明人： Timothy Pontius ,  Robert L. Payne ,  David R. Evoy

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L7/02 ,  G06F5/10 ,  G06F2205/102 ,  H04L7/0008 ,  H04L7/005

摘要： A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

摘要翻译： 提供了将数据从源时钟域传递到非同步接收时钟域的方法和装置。 位于源时钟域的第一处理电路将写入地址信息与数据相连接，并且时钟发生器在与源时钟同步的源时钟域中生成发送时钟信号。 第一处理电路将时钟信号和具有链接的写入地址信息的数据发送到接收时钟域中的第二处理电路。 在接收时钟域中，第二处理电路将数据写入指定对应于链接的写入地址信息的存储元件的地址。 第二处理电路响应于来自源时钟域的写入使能信号将数据与伴随的发送时钟信号同步地存储到存储元件中，并且从存储元件读出与接收域时钟同步的数据。

公开(公告)号：US06996106B2

公开(公告)日：2006-02-07

申请号：US09997609

申请日：2001-11-29

申请人： Robert L. Payne ,  David R. Evoy ,  Timothy Pontius ,  George Ellis Spatz

发明人： Robert L. Payne ,  David R. Evoy ,  Timothy Pontius ,  George Ellis Spatz

IPC分类号： H04L12/28

CPC分类号： G06F13/126

摘要： A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.

公开(公告)号：US06839862B2

公开(公告)日：2005-01-04

申请号：US09871159

申请日：2001-05-31

申请人： David R. Evoy ,  Timothy Pontius ,  Gregory E. Ehmann

发明人： David R. Evoy ,  Timothy Pontius ,  Gregory E. Ehmann

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L25/02 ,  H04L25/14 ,  G06F1/04 ,  G06F1/12 ,  G04L7/00

CPC分类号： H04L7/0008 ,  H04L25/14

摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.

摘要翻译： 在一个示例实施例中，高速并行数据通信方法通过包括多个并行数据携带线路和时钟路径的通信信道将数字数据从第一模块并行传送到第二模块。 并行总线布置成多个组，每个组包括多个数据传送线和适于承载时钟信号的时钟路径，用于将从第一模块承载的数字数据同步到第二模块。 使用并行总线的线路并行传送数据组，并且在第二模块处，并且对于每个组，经由该组的时钟信号同步地收集传送的数字数据。 在第二个模块中，对每个组收集的数据进行对齐。 通过将每个组具有自己的时钟域的组中的总线分组，通过在每个时钟域组内，然后在组之间首先处理数据和偏移来容忍和克服时钟域组之间的偏斜。

公开(公告)号：US06636166B2

公开(公告)日：2003-10-21

申请号：US09871197

申请日：2001-05-31

申请人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

发明人： D. C. Sessions ,  Robert J. Caesar, Jr. ,  Ivan Svestka ,  David R. Evoy ,  Timothy Pontius ,  Mark Johnson ,  Arjan Bink

IPC分类号： H03M700

CPC分类号： H04L25/4908 ,  H04L25/14

摘要： In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

公开(公告)号：US08230289B2

公开(公告)日：2012-07-24

申请号：US12161674

申请日：2006-11-14

申请人： Ewa Hekstra-Nowacka ,  Andrei Radulescu ,  David R. Evoy

发明人： Ewa Hekstra-Nowacka ,  Andrei Radulescu ,  David R. Evoy

IPC分类号： G08C25/02 ,  H04L1/18

CPC分类号： G06F15/17 ,  H04L1/1877 ,  H04L1/1887

摘要： A data processor system includes a first data processor unit for transmitting data units to a second data processor unit and a retry buffer for temporarily storing transmitted data units. The second data processor unit receives the transmitted data and includes an error detector for detecting an error in the received data. When an error is detected, the first data processor unit is notified and a controller causes a data selector to select data from a retry buffer. The first data processor unit limits retransmission of a data unit to a predetermined maximum number of times irrespective of whether the data unit is correctly received or not. This allows for an undisturbed flow of streaming data with an increased reliability.

摘要翻译： 数据处理器系统包括用于将数据单元发送到第二数据处理器单元的第一数据处理器单元和用于临时存储发送数据单元的重试缓冲器。 第二数据处理器单元接收所发送的数据，并且包括用于检测接收到的数据中的错误的错误检测器。 当检测到错误时，通知第一数据处理器单元，并且控制器使数据选择器从重试缓冲器中选择数据。 第一数据处理器单元将数据单元的重传限制到预定的最大次数，而不管数据单元是否被正确接收。 这允许流量数据的流量不受干扰，并具有增加的可靠性。

公开(公告)号：US08004922B2

公开(公告)日：2011-08-23

申请号：US12479517

申请日：2009-06-05

申请人： David R. Evoy ,  Peter Klapporth ,  Jose J. Pineda De Gyvez

发明人： David R. Evoy ,  Peter Klapporth ,  Jose J. Pineda De Gyvez

IPC分类号： G11C7/00

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics.

摘要翻译： 用于片上系统（SoC）的功率岛包括第一段，第二段和供电线。 第一段包括硬件设备，并以指示至少第一电压的第一功率特性来操作硬件设备。 第二段包括可伸缩逻辑，并以指示至少第二电压的第二功率特性来操作可伸缩逻辑。 可伸缩逻辑的第二功率特性与硬件设备的第一功率特性不同。 电源线接收外部电源信号（VDD），并将外部电源信号引导到第一段和第二段。 第二段改变外部电源信号的至少一个功率特性，以根据第二功率特性来操作可伸缩逻辑。

公开(公告)号：US20100107008A1

公开(公告)日：2010-04-29

申请号：US12449442

申请日：2008-01-31

申请人： Andrei Radulescu ,  David R. Evoy

发明人： Andrei Radulescu ,  David R. Evoy

IPC分类号： G06F11/14 ,  G06F11/07

CPC分类号： H04L1/1877 ,  H04L1/1635 ,  H04L1/1642 ,  H04L1/1848

摘要： A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data already present in the retransmission buffer is overwritten, selecting the one or more oldest data frames in the retransmission buffer to be overwritten, in case an error is determined in the received data frame, communicating an error message to the transmitter of the data frame, which error message at least comprises an indication of the sequence number of the last correctly received data frame—upon receipt of such message and if available, retransmitting one or more data frames from the retransmission buffer having a sequence number higher than the sequence number communicated in the message.

摘要翻译： 描述了发送数据的方法，包括以下步骤：产生用于发送的数据帧，包括序列号和用户数据的数据帧，在重发缓冲器中保存数据帧的副本，以及如果所述保存步骤 复制要求重写缓冲区中已经存在的数据被覆盖，在接收到的数据帧中确定错误的情况下，选择要重写的重发缓冲器中的一个或多个最旧的数据帧，向错误消息传送错误消息 数据帧，该错误消息至少包括最后正确接收的数据帧的序列号的指示 - 在接收到这样的消息时，如果可用，则从具有高于序列的序列号的重发缓冲器重发一个或多个数据帧 消息中传达的号码。

公开(公告)号：US20080256284A1

公开(公告)日：2008-10-16

申请号：US10592191

申请日：2005-03-21

申请人： David R. Evoy ,  Jeremy Michael Rose

发明人： David R. Evoy ,  Jeremy Michael Rose

IPC分类号： G06F13/00 ,  G06F17/50

CPC分类号： G06F13/4022

摘要： Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices.

摘要翻译： 呈现出两个看起来是分层的两个独立的硬件子系统的软件视图的单个硬件子系统是用PCI类型安排来实现的。 根据本发明的示例实施例，硬件布置适于在单个硬件块中模拟两个实际上分离的分层子系统。 这种仿真有助于将设备耦合到PCI Express型通信链路，同时解决这些设备的PCI-Express类型链接要求。

公开(公告)号：US06766460B1

公开(公告)日：2004-07-20

申请号：US09645468

申请日：2000-08-23

申请人： David R. Evoy ,  Lonnie C. Goff ,  Bonnie Sexton

发明人： David R. Evoy ,  Lonnie C. Goff ,  Bonnie Sexton

IPC分类号： G06F128

CPC分类号： G06F9/3879 ,  G06F1/3203

摘要： A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.

摘要翻译： 公开了一种为基于硬件的Java加速器提供功率管理的功率管理方法。 最初，响应于启动Java应用程序，从主机处理器提供Java模式信号。 此后，减少了对主处理器的电力，并且响应于Java模式信号而增加了对Java处理器的供电。 然后，当Java应用程序的执行停止时，从Java处理器生成Java完成信号，从而发信号通知系统将控制返回到主机处理器。

公开(公告)号：US06105142A

公开(公告)日：2000-08-15

申请号：US799099

申请日：1997-02-11

申请人： Lonnie C. Goff ,  David R. Evoy ,  Franklyn Story ,  Mark Sullivan

发明人： Lonnie C. Goff ,  David R. Evoy ,  Franklyn Story ,  Mark Sullivan

IPC分类号： G06F1/32 ,  G06F9/46

CPC分类号： G06F9/46 ,  G06F1/3203

摘要： A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration and Power Interface (ACPI) specification. In one embodiment, a power management processor is sandwiched between platform hardware and the ACPI register layer. The processor processes all operating power management commands and requests while remaining transparent to the user and the operating system. In so doing, routine power management functions, so classified by the operating system, are implemented by the operating system. Sophisticated power management features, on the other hand, are implemented by the present invention independent from operating system control. Accordingly, in the present invention, the operating system need not suspend processing of other threads to process sophisticated power management procedures.

摘要翻译： 一种用于管理计算机系统中的功耗的方法和装置，其中所述方法和装置符合所提出的高级配置和电源接口（ACPI）规范。 在一个实施例中，电源管理处理器夹在平台硬件和ACPI寄存器层之间。 处理器处理所有操作电源管理命令和请求，同时对用户和操作系统保持透明。 这样做，由操作系统分类的日常电源管理功能由操作系统实现。 另一方面，复杂的电源管理功能由独立于操作系统控制的本发明实现。 因此，在本发明中，操作系统不需要暂停其他线程的处理来处理复杂的电源管理过程。