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    Fusion of processor micro-operations
    3.
    发明授权
    Fusion of processor micro-operations 有权
    处理器微操作的融合

    公开(公告)号：US06920546B2

    公开(公告)日：2005-07-19

    申请号：US10217033

    申请日：2002-08-13

    申请人： Simcha Gochman ,  Ittai Anati ,  Zeev Sperber ,  Robert Valentine

    发明人： Simcha Gochman ,  Ittai Anati ,  Zeev Sperber ,  Robert Valentine

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/383

    摘要： Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.

    摘要翻译： 方法和系统提供将多个操作融合到单个微操作（uop）中。 解码宏指令的方法提供将与第一操作有关的数据从宏指令传送到uop。 uop将由处理器的执行系统执行。 该方法还提供将与第二操作有关的数据从宏指令传送到uop。

    Processor and methods to reduce power consumption of processor components
    6.
    发明申请
    Processor and methods to reduce power consumption of processor components 审中-公开

    公开(公告)号：US20070088965A1

    公开(公告)日：2007-04-19

    申请号：US11637064

    申请日：2006-12-12

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    Processor and methods to reduce power consumption of procesor components
    7.
    发明申请
    Processor and methods to reduce power consumption of procesor components 失效
    处理器和减少处理器组件功耗的方法

    公开(公告)号：US20050081067A1

    公开(公告)日：2005-04-14

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下工作，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

    Processor and methods to reduce power consumption of processor components
    8.
    发明授权
    Processor and methods to reduce power consumption of processor components 失效
    处理器和方法来降低处理器组件的功耗

    公开(公告)号：US07167989B2

    公开(公告)日：2007-01-23

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F9/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下运行，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

    Efficient parallel floating point exception handling in a processor
    9.
    发明授权
    Efficient parallel floating point exception handling in a processor 有权
    处理器中的高效并行浮点异常处理

    公开(公告)号：US08103858B2

    公开(公告)日：2012-01-24

    申请号：US12217084

    申请日：2008-06-30

    申请人： Zeev Sperber ,  Shachar Finkelstein ,  Gregory Pribush ,  Arnit Gradstein ,  Guy Bale ,  Thierry Pons

    发明人： Zeev Sperber ,  Shachar Finkelstein ,  Gregory Pribush ,  Arnit Gradstein ,  Guy Bale ,  Thierry Pons

    IPC分类号： G06F9/00

    CPC分类号： G06F9/3861 ,  G06F9/30014 ,  G06F9/30036

    摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译： 公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。 在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

    Efficient parallel floating point exception handling in a processor
    10.
    发明申请
    Efficient parallel floating point exception handling in a processor 有权
    处理器中的高效并行浮点异常处理

    公开(公告)号：US20090327665A1

    公开(公告)日：2009-12-31

    申请号：US12217084

    申请日：2008-06-30

    申请人： Zeev Sperber ,  Shachar Finkelstein ,  Gregory Pribush ,  Amit Gradstein ,  Guy Bale ,  Thierry Pons

    发明人： Zeev Sperber ,  Shachar Finkelstein ,  Gregory Pribush ,  Amit Gradstein ,  Guy Bale ,  Thierry Pons

    IPC分类号： G06F9/302

    CPC分类号： G06F9/3861 ,  G06F9/30014 ,  G06F9/30036

    摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.

    摘要翻译： 公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。 在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。 启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。 标志被设置和存储与打包部分结果以识别异常元素。 在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。