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    Fusion of processor micro-operations
    1.
    发明授权
    Fusion of processor micro-operations 有权
    处理器微操作的融合

    公开(公告)号：US06920546B2

    公开(公告)日：2005-07-19

    申请号：US10217033

    申请日：2002-08-13

    申请人： Simcha Gochman ,  Ittai Anati ,  Zeev Sperber ,  Robert Valentine

    发明人： Simcha Gochman ,  Ittai Anati ,  Zeev Sperber ,  Robert Valentine

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/00

    CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/383

    摘要： Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.

    摘要翻译： 方法和系统提供将多个操作融合到单个微操作（uop）中。 解码宏指令的方法提供将与第一操作有关的数据从宏指令传送到uop。 uop将由处理器的执行系统执行。 该方法还提供将与第二操作有关的数据从宏指令传送到uop。

    Micro-operation un-lamination
    2.
    发明授权
    Micro-operation un-lamination 有权
    微操作分层

    公开(公告)号：US07206921B2

    公开(公告)日：2007-04-17

    申请号：US10407468

    申请日：2003-04-07

    申请人： Zeev Sperber ,  Robert Valentine ,  Simcha Gochman

    发明人： Zeev Sperber ,  Robert Valentine ,  Simcha Gochman

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3017 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

    摘要： A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.

    摘要翻译： 处理器可以包括用于将宏指令解码为微操作的指令解码器。 在一些实施例中，指令解码器可以包括第一解码器和第二解码器。 第一解码器可以将具有SSE数据类型操作数的宏指令解码为层叠微操作，并且可以生成层叠微操作的未分层信息。 第二解码器可以从层叠微操作和非分层信息生成两个或多个微操作，其中两个或多个微操作的操作数分别对应于宏指令的一个SSE操作数中的一个。

    Processor and methods to reduce power consumption of processor components
    7.
    发明申请
    Processor and methods to reduce power consumption of processor components 审中-公开

    公开(公告)号：US20070088965A1

    公开(公告)日：2007-04-19

    申请号：US11637064

    申请日：2006-12-12

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    Processor and methods to reduce power consumption of procesor components
    8.
    发明申请
    Processor and methods to reduce power consumption of procesor components 失效
    处理器和减少处理器组件功耗的方法

    公开(公告)号：US20050081067A1

    公开(公告)日：2005-04-14

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下工作，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

    Processor and methods to reduce power consumption of processor components
    9.
    发明授权
    Processor and methods to reduce power consumption of processor components 失效
    处理器和方法来降低处理器组件的功耗

    公开(公告)号：US07167989B2

    公开(公告)日：2007-01-23

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F9/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下运行，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。