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1.发明授权Method for manufacturing dual work function gate electrodes through local thickness-limited silicidation 有权通过局部厚度限制硅化物制造双功能功能栅电极的方法公开(公告)号：US07338865B2
公开(公告)日：2008-03-04
申请号：US10897846
申请日：2004-07-23
申请人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
发明人： Robert W. Murto , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823835 , H01L21/823842
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
摘要翻译： 本发明提供一种制造半导体器件的方法。 除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135） 位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上并且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函 随之而来。
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公开(公告)号：US08021990B2
公开(公告)日：2011-09-20
申请号：US12421036
申请日：2009-04-09
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L21/823871 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
摘要翻译： 一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。
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3.发明申请TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER 审中-公开使用物理蒸气沉积层和化学气相沉积层创建门电极的两步法公开(公告)号：US20100155860A1
公开(公告)日：2010-06-24
申请号：US12344046
申请日：2008-12-24
IPC分类号： H01L29/43 , H01L21/283 , H01L21/336 , C23C14/34
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode.
摘要翻译： 本发明的一个实施例涉及通过利用用于形成栅电极的两步沉积方法形成的半导体器件，而不会对下面的栅介质材料造成损害。 在一个实施例中，使用不损坏栅极电介质材料（例如，物理气相沉积）的沉积，在栅极电介质材料的表面上形成第一层栅电极材料（第一栅电极层），从而导致损坏 栅介电材料和栅电极材料之间的自由界面。 然后使用提供增加的沉积控制（例如，良好的层均匀性，杂质控制等）的化学沉积方法将第二层栅电极材料（第二栅极电极层）形成在第一层栅电极材料层上。 然后，第一和第二栅极电极层被选择性地图案化以累积地形成半导体器件的栅电极。
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公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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5.发明授权High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权具有均匀氮分布的高k栅极电介质及其制造方法公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译： 提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。
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6.发明授权Method for fabricating transistor gate structures and gate dielectrics thereof 有权制造晶体管栅极结构及其栅极电介质的方法公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。
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7.发明授权Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译： 具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。
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8.发明授权Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极公开(公告)号：US07109077B2
公开(公告)日：2006-09-19
申请号：US10301224
申请日：2002-11-21
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译： 在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。 在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。 多晶硅层可以包含0至50原子％的锗。 在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。 蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。 如果需要，可以在金属栅极结构上方形成包覆层（100）。
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公开(公告)号：US07105891B2
公开(公告)日：2006-09-12
申请号：US10195271
申请日：2002-07-15
IPC分类号： H01L29/94
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/823842
摘要： CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
摘要翻译： 具有金属栅极的CMOS栅极结构具有由NMOS和PMOS栅极之间的纹理差异而具有不同功函数。
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10.发明授权Refractory metal-based electrodes for work function setting in semiconductor devices 有权用于半导体器件功能设置的耐火金属基电极公开(公告)号：US07098516B2
公开(公告)日：2006-08-29
申请号：US10852523
申请日：2004-05-24
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译： 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。
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