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1.发明授权Method for fabricating transistor gate structures and gate dielectrics thereof 有权制造晶体管栅极结构及其栅极电介质的方法公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。
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公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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3.发明授权High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权具有均匀氮分布的高k栅极电介质及其制造方法公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译： 提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。
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公开(公告)号：US06852645B2
公开(公告)日：2005-02-08
申请号：US10367429
申请日：2003-02-13
IPC分类号： C23C28/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78 , H01L21/469
CPC分类号： H01L21/28185 , C23C28/00 , H01L21/02238 , H01L21/02255 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31155 , H01L21/31662 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.
摘要翻译： 本发明涉及在制造半导体器件时形成适用于高k栅极电介质的高品质薄界面氧化物层的方法。 使用含有氧和还原剂的环境来生长层。 氧促进层的生长，而还原剂同时抵消该生长。 因此，可以通过调节还原剂的分压来控制层的生长速度，还原剂的分压是气相中还原剂的分数乘以总压力。 控制和减缓层的生长速率有助于在约850摄氏度或更高的温度下将层的生产达到约10埃或更小的厚度。 在高温下生长层有助于更好地粘合和生产更高质量的层，这又产生更好的性能和更可靠的结果产品。
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公开(公告)号：US07291890B2
公开(公告)日：2007-11-06
申请号：US11339393
申请日：2006-01-25
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.
摘要翻译： 具有高k栅极电介质层和硅或金属栅极的MOSFET结构，与等离子体或离子注入一起对高k栅极介电层进行非晶化处理。
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公开(公告)号：US06797599B2
公开(公告)日：2004-09-28
申请号：US10232124
申请日：2002-08-30
IPC分类号： H01L213205
CPC分类号： H01L21/28185 , H01L21/28114 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/823857 , H01L29/42376 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material desposition and gate formation.
摘要翻译： 一种具有高k栅极介质的MOSFSET结构，用于在栅极材料沉积和栅极形成之前的栅极介质液体氧化表面处理的硅或金属栅极。
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7.发明授权Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极公开(公告)号：US07109077B2
公开(公告)日：2006-09-19
申请号：US10301224
申请日：2002-11-21
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译： 在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。 在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。 多晶硅层可以包含0至50原子％的锗。 在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。 蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。 如果需要，可以在金属栅极结构上方形成包覆层（100）。
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公开(公告)号：US07105891B2
公开(公告)日：2006-09-12
申请号：US10195271
申请日：2002-07-15
IPC分类号： H01L29/94
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/823842
摘要： CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
摘要翻译： 具有金属栅极的CMOS栅极结构具有由NMOS和PMOS栅极之间的纹理差异而具有不同功函数。
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9.发明授权Method of making multiple work function gates by implanting metals with metallic alloying additives 有权通过金属合金添加剂注入金属制作多功能门的方法公开(公告)号：US06770521B2
公开(公告)日：2004-08-03
申请号：US10135725
申请日：2002-04-29
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A method of forming a first and second transistors with differing work function gates by differing metals with a second metal selectively implanted or diffused into a first metal.
摘要翻译： 通过不同金属形成具有不同功函数栅极的第一和第二晶体管的方法，其中第二金属选择性地注入或扩散到第一金属中。
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公开(公告)号：US08021990B2
公开(公告)日：2011-09-20
申请号：US12421036
申请日：2009-04-09
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/823857 , H01L21/823871 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
摘要翻译： 一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。
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