公开(公告)号：US08367552B2

公开(公告)日：2013-02-05

申请号：US10526422

申请日：2003-08-04

申请人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

发明人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/7684 ,  H01L21/7688

摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料的基底，在电介质材料的顶部上沉积保护层，在保护层的顶部上沉积牺牲层，牺牲层的机械强度低于 保护层的机械强度，形成开口）穿过保护层并进入电介质材料，在开口和牺牲层上沉积阻挡层，在阻挡层上沉积金属材料，金属 填充开口的材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层。

公开(公告)号：US08310053B2

公开(公告)日：2012-11-13

申请号：US12427797

申请日：2009-04-22

申请人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

发明人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

IPC分类号： H01L23/522 ,  H01L21/4763 ,  H01L21/473

CPC分类号： H02N1/00 ,  B81C1/00476 ,  H01L21/02 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/50 ,  H01L21/7688 ,  H01L29/84

摘要： A micro-device with a cavity, the micro-device including a substrate. A method of forming the micro-device includes the steps of: A) providing the substrate having a surface and comprising a sacrificial oxide region at the surface; B) covering the sacrificial oxide region with a porous layer being permeable to a vapor HF etchant; and C) selectively etching the sacrificial oxide region through the porous layer using the vapor HF etchant to obtain the cavity. This method may be used in the manufacture of various micro-devices with a cavity , i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

摘要翻译： 具有空腔的微器件，微器件包括衬底。 形成微器件的方法包括以下步骤：A）提供具有表面并且在表面包括牺牲氧化物区域的衬底; B）覆盖牺牲氧化物区域，多孔层可透过蒸汽HF蚀刻剂; 并且C）使用蒸汽HF蚀刻剂选择性地蚀刻通过多孔层的牺牲氧化物区域以获得空腔。 该方法可以用于制造具有腔体的各种微器件，即MEMS器件，特别是其封装部件，以及半导体器件，特别是其BEOL部件。

公开(公告)号：US20090267166A1

公开(公告)日：2009-10-29

申请号：US12427797

申请日：2009-04-22

申请人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

发明人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

IPC分类号： H01L29/84 ,  H01L21/50

CPC分类号： H02N1/00 ,  B81C1/00476 ,  H01L21/02 ,  H01L21/02126 ,  H01L21/31116 ,  H01L21/50 ,  H01L21/7688 ,  H01L29/84

摘要： The invention relates to a micro-device with a cavity (50), the micro-device comprising a substrate (10, 110), the method comprising steps of: A) providing the substrate (10, 110), having a surface and comprising a sacrificial oxide region (20, 107, 115) at the surface ( ); B) covering the sacrificial oxide region (20, 107, 115) with a porous layer (40, 114, 124) being permeable to a vapor HF etchant (100), and C) selectively etching the sacrificial oxide region (20, 107, 115) through the porous layer (40, 114, 124) using the vapor HF etchant (100) to obtain the cavity (50). This method may be used in the manufacture of various micro-devices with a cavity (50), i.e. MEMS devices, and in particular in the encapsulation part thereof, and semiconductor devices, and in particular the BEOL-part thereof.

摘要翻译： 本发明涉及具有空腔（50）的微器件，该微器件包括衬底（10,110），该方法包括以下步骤：A）提供具有表面的衬底（10,110），其包括 在表面（）处的牺牲氧化物区域（20,107,115）; B）用可透气体HF蚀刻剂（100）的多孔层（40,114,124）覆盖所述牺牲氧化物区域（20,107,115），以及C）选择性地蚀刻所述牺牲氧化物区域（20,107,115） 115）通过使用蒸汽HF蚀刻剂（100）的多孔层（40,114,124）获得空腔（50）。 该方法可以用于制造具有空腔（50）的各种微器件，即MEMS器件，特别是其封装部分，以及半导体器件，特别是其BEOL部分。

公开(公告)号：US20100006957A1

公开(公告)日：2010-01-14

申请号：US12477798

申请日：2009-06-03

申请人： Greja Johanna Adriana Maria VERHEIJDEN ,  Roel Daamen ,  Gerhard Koops

发明人： Greja Johanna Adriana Maria VERHEIJDEN ,  Roel Daamen ,  Gerhard Koops

IPC分类号： H01L29/84 ,  H01L21/30

CPC分类号： B81C1/00293 ,  B81C2201/0115 ,  B81C2203/0136 ,  B81C2203/0145

摘要： A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.

摘要翻译： 公开了一种封装微机电结构的方法。 该方法包括以下步骤：在衬底上形成结构，在结构上沉积牺牲层，图案化牺牲层，在图案化的牺牲层上沉积多孔层，通过多孔层去除图案化的牺牲层，处理多孔层 并在等离子体处理的多孔层上沉积覆盖层。 等离子体处理步骤确保了封盖层材料不能进入通过多孔层去除牺牲层而形成的空腔。 还公开了通过该方法形成的器件。

公开(公告)号：US08273653B2

公开(公告)日：2012-09-25

申请号：US12477798

申请日：2009-06-03

申请人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

发明人： Greja Johanna Adriana Maria Verheijden ,  Roel Daamen ,  Gerhard Koops

IPC分类号： H01L21/00

CPC分类号： B81C1/00293 ,  B81C2201/0115 ,  B81C2203/0136 ,  B81C2203/0145

摘要： A method of packaging a micro electromechanical structure is disclosed. The method comprises the steps of forming the structure on a substrate, depositing a sacrificial layer over the structure, patterning the sacrificial layer, depositing a porous layer over the patterned sacrificial layer, removing the patterned sacrificial layer through the porous layer, treating the porous layer with a plasma and depositing a capping layer over the plasma-treated porous layer. The plasma treatment step ensures that the capping layer material cannot enter the cavity formed by the removal of the sacrificial layer through the porous layer. A device formed by this method is also disclosed.

摘要翻译： 公开了一种封装微机电结构的方法。 该方法包括以下步骤：在衬底上形成结构，在结构上沉积牺牲层，图案化牺牲层，在图案化的牺牲层上沉积多孔层，通过多孔层去除图案化的牺牲层，处理多孔层 并在等离子体处理的多孔层上沉积覆盖层。 等离子体处理步骤确保了封盖层材料不能进入通过多孔层去除牺牲层而形成的空腔。 还公开了通过该方法形成的器件。

公开(公告)号：US07589425B2

公开(公告)日：2009-09-15

申请号：US11084081

申请日：2005-03-17

申请人： Roel Daamen ,  Greja Johanna Adriana Maria Verheijden

发明人： Roel Daamen ,  Greja Johanna Adriana Maria Verheijden

IPC分类号： H01L29/40 ,  H01L21/4763

CPC分类号： H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.

摘要翻译： 提供一种制造具有气隙的镶嵌结构的半导体器件的方法。 在一个实施例中，该方法包括提供具有第一金属层的基本上平坦的层，沉积通孔层介电层，图案化通孔层电介质层，至少部分刻蚀通孔层电介质层，至少在至少 图案化一次性层，沉积第二金属层，平面化第二金属层，在平坦化第二金属层之后沉积可渗透介电层，以及通过可渗透介电层去除一次性层以形成气隙。

公开(公告)号：US07709387B2

公开(公告)日：2010-05-04

申请号：US10544411

申请日：2004-01-23

申请人： Viet Nguyen Hoang ,  Roel Daamen

发明人： Viet Nguyen Hoang ,  Roel Daamen

IPC分类号： H01L21/302

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： The method of manufacturing an integrated circuit (IC) according to the invention starts with providing a pre-fabricated integrated circuit (10) comprising an electrical device (2) and having a surface (11) coated with a dielectric material (12) and a metal (15). The dielectric material (12), which may be separated from the metal (15) by the barrier layer (14), has an opening (13), which is filled with the metal (15). Portions of the metal (15) outside the opening (13) are removed by polishing for a first period of time, after which an etching agent (25) is added to the polishing liquid (24) and polishing is continued for a second period of time for removing portions of the metal (15) remaining outside the opening (13). The polishing apparatus (40) is able to perform the method.

摘要翻译： 根据本发明的制造集成电路（IC）的方法开始于提供一种包括电气装置（2）并具有涂覆有电介质材料（12）的表面（11）的预制集成电路（10）和 金属（15）。 可以通过阻挡层（14）与金属（15）分离的电介质材料（12）具有填充有金属（15）的开口（13）。 通过在第一时间内抛光除去开口（13）外部的金属部分（15），然后将蚀刻剂（25）加入到抛光液体（24）中，继续研磨第二周期 用于去除剩余在开口（13）外部的金属（15）的部分的时间。 抛光装置（40）能够执行该方法。

公开(公告)号：US07510959B2

公开(公告)日：2009-03-31

申请号：US11083344

申请日：2005-03-16

申请人： Roel Daamen ,  Viet Nguyen Hoang

发明人： Roel Daamen ,  Viet Nguyen Hoang

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682

摘要： A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

摘要翻译： 提供一种制造具有气隙的镶嵌结构的半导体器件的方法。 在一个实施例中，该方法包括以下步骤：沉积和图案化一次性层，在图案化的一次性层的顶部上沉积第一阻挡层，沉积金属层，平坦化金属层，沉积第二阻挡层，平坦化第二屏障 层，直到在一次性层的顶部上基本上没有阻挡层材料，沉积可渗透层，通过可渗透层去除一次性层以形成气隙。

公开(公告)号：US20110097896A1

公开(公告)日：2011-04-28

申请号：US10526422

申请日：2003-08-04

申请人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

发明人： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

IPC分类号： H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/7688

摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material (1) on top thereof, depositing a protection layer (2) on top of the dielectric material, depositing a sacrificial layer (7) on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening (3) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer (4) in the opening and on the sacrificial layer, depositing metal material (5) on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料（1）的基底，在电介质材料的顶部上沉积保护层（2），在保护层的顶部上沉积牺牲层（7） 具有低于保护层的机械强度的机械强度的层，通过保护层形成通过牺牲层的开口（3）并进入电介质材料，在开口中沉积阻挡层（4） 牺牲层，在阻挡层上沉积金属材料（5），填充开口的金属材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层 。

公开(公告)号：US08963563B2

公开(公告)日：2015-02-24

申请号：US12969884

申请日：2010-12-16

申请人： Aurelie Humbert ,  Matthias Merz ,  Youri Victorovitch Ponomarev ,  Roel Daamen ,  Marcus Johannes Henricus van Dal

发明人： Aurelie Humbert ,  Matthias Merz ,  Youri Victorovitch Ponomarev ,  Roel Daamen ,  Marcus Johannes Henricus van Dal

IPC分类号： G01N27/22 ,  G01R27/26

CPC分类号： G01N27/223 ,  G01R27/2605

摘要： A capacitive sensor for detecting the presence of a substance includes a plurality of upstanding conductive pillars arranged within a first layer of the sensor, a first electrode connected to a first group of the pillars, a second electrode connected to a second, different group of the pillars, and a dielectric material arranged adjacent the pillars, for altering the capacitance of the sensor in response to the presence of said substance.

摘要翻译： 用于检测物质存在的电容传感器包括布置在传感器的第一层内的多个直立的导电柱，连接到第一组柱的第一电极，连接到第二组不同组的第二电极 支柱和邻近柱子布置的介电材料，用于响应于所述物质的存在而改变传感器的电容。