Method for producing a floating gate memory structure
    1.
    发明授权
    Method for producing a floating gate memory structure 有权
    浮栅存储器结构的制造方法

    公开(公告)号:US08865582B2

    公开(公告)日:2014-10-21

    申请号:US13280546

    申请日:2011-10-25

    摘要: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.

    摘要翻译: 公开了用于制造如此制造的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中,该方法包括提供单晶半导体衬底,在衬底上形成隧道氧化物层,以及在隧道氧化物层上沉积保护层以形成隧道氧化物层和保护层的堆叠。 该方法还包括在堆叠中形成至少一个开口,从而暴露基板的至少一部分,以及用清洗液清洁至少一个暴露部分。 该方法还包括将包含该叠层的衬底加载到反应器中,此后,使用至少一个暴露部分作为源外延生长包含单晶半导体材料的层,然后进行原位蚀刻以去除保护层 ,并且将该层形成至少一个柱状浮栅结构。

    Method for producing a floating gate memory structure
    2.
    发明申请
    Method for producing a floating gate memory structure 有权
    浮栅存储器结构的制造方法

    公开(公告)号:US20120112262A1

    公开(公告)日:2012-05-10

    申请号:US13280546

    申请日:2011-10-25

    IPC分类号: H01L29/788 H01L21/336

    摘要: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.

    摘要翻译: 公开了用于制造如此制造的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中,该方法包括提供单晶半导体衬底,在衬底上形成隧道氧化物层,以及在隧道氧化物层上沉积保护层以形成隧道氧化物层和保护层的堆叠。 该方法还包括在堆叠中形成至少一个开口,从而暴露基板的至少一部分,以及用清洗液清洁至少一个暴露部分。 该方法还包括将包含该叠层的衬底加载到反应器中,此后,使用至少一个暴露部分作为源外延生长包含单晶半导体材料的层,然后进行原位蚀刻以去除保护层 ,并且将该层形成至少一个柱状浮栅结构。

    Method for selective deposition of a semiconductor material
    3.
    发明授权
    Method for selective deposition of a semiconductor material 有权
    选择性沉积半导体材料的方法

    公开(公告)号:US08709918B2

    公开(公告)日:2014-04-29

    申请号:US13351344

    申请日:2012-01-17

    IPC分类号: H01L21/20

    摘要: A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.

    摘要翻译: 公开了一种在半导体处理中选择性沉积半导体材料的方法。 在一些实施例中,该方法包括提供包括第一区域和第二区域的图案化衬底,其中第一区域包括暴露的第一半导体材料,第二区域包括暴露的绝缘体材料。 该方法还包括通过提供第二半导体材料的前体,与氯化合物不反应的载气和四氯化锡(SnCl 4),选择性地在第一区域的第一半导体材料上提供第二半导体材料的膜, 。 四氯化锡抑制第二半导体材料沉积在第二区域的绝缘体材料上。

    Method for direct deposition of a germanium layer
    4.
    发明授权
    Method for direct deposition of a germanium layer 有权
    直接沉积锗层的方法

    公开(公告)号:US08530339B2

    公开(公告)日:2013-09-10

    申请号:US13347834

    申请日:2012-01-11

    IPC分类号: H01L29/16

    摘要: The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH4), is applied. In an example embodiment, the deposition is done under application of a deposition temperature between 275° C. and 500° C., with the partial pressure of the precursor gas within the mixture being at least 20 mTorr for temperatures between 275° C. and 285° C., and at least 10 mTorr for temperatures between 285° and 500° C.

    摘要翻译: 本公开涉及通过化学气相沉积在基底上沉积锗的连续层的方法。 根据本公开,应用非反应性载气和高级锗前体气体,即高于锗烷(GeH 4)的混合物。 在一个示例性实施例中,沉积在275℃至500℃之间的沉积温度下进行,混合物中前体气体的分压至少为20mTorr,温度为275℃至 285°C,至少10 mTorr,温度在285°和500°C之间。

    Method for manufacturing a junction
    5.
    发明授权
    Method for manufacturing a junction 有权
    接头的制造方法

    公开(公告)号:US08158451B2

    公开(公告)日:2012-04-17

    申请号:US12647773

    申请日:2009-12-28

    IPC分类号: H01L21/00

    摘要: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.

    摘要翻译: 本发明涉及包含具有受控掺杂剂(浓度)分布的均质结或异质结的半导体器件及其制造方法。 因此,本发明的一个方面是一种用于制造接合部的方法,包括形成包含第一浓度的第一掺杂剂的第一半导体材料; 形成包含第二掺杂剂的第二半导体材料,其具有第二浓度从而形成结,并且通过原子层外延或气相掺杂使至少一部分适于在第一半导体材料上形成第二掺杂剂的前体单层的单层沉积 在形成第二半导体材料之前,从而增加第二掺杂剂在该结处的第二浓度。

    Method for Doping Semiconductor Structures and the Semiconductor Device Thereof
    6.
    发明申请
    Method for Doping Semiconductor Structures and the Semiconductor Device Thereof 有权
    掺杂半导体结构的方法及其半导体器件

    公开(公告)号:US20110169049A1

    公开(公告)日:2011-07-14

    申请号:US13002749

    申请日:2009-07-06

    IPC分类号: H01L29/78 H01L21/22 H01L29/12

    摘要: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.

    摘要翻译: 一种用于将物质引入应变半导体层的方法,包括:提供包括包含暴露的应变半导体层的第一区域的衬底,将衬底加载到反应室中,然后通过气相沉积(VPD)形成保形的第一种容纳层, 至少在暴露的应变半导体层上,然后进行热处理,从而使至少部分第一种类从第一种含有层扩散到应变半导体层中,并激活至少部分扩散的第一种类在应变半导体层 半导体层。

    METHOD TO IMPROVE THE SELECTIVE EPITAXIAL GROWTH (SEG) PROCESS
    8.
    发明申请
    METHOD TO IMPROVE THE SELECTIVE EPITAXIAL GROWTH (SEG) PROCESS 审中-公开
    提高选择性外延生长(SEG)过程的方法

    公开(公告)号:US20080153266A1

    公开(公告)日:2008-06-26

    申请号:US11962020

    申请日:2007-12-20

    IPC分类号: H01L21/20

    摘要: A method of producing a semiconductor device using a selective epitaxial growth (SEG) process is disclosed. In one aspect, the method comprises providing a semiconductor substrate, forming a pattern of an insulation material on the semiconductor substrate, thereby defining a covered and non covered surface, performing a cleaning processing of the covered and non covered surface of the substrate having the insulating pattern defined, loading the substrate with the insulating pattern into a reaction chamber of an epitaxial reactor, and starting a selective epitaxial growth comprising an injection of at least one semiconductor source gas possibly with at least one first carrier gas in the reaction chamber of the epitaxial reactor. The method further comprises, prior to the selective epitaxial growth, the surface of the substrate is subjected in the reaction chamber to an in situ pre-treatment with the injection of a halogen containing etching gas possibly with a second carrier gas.

    摘要翻译: 公开了使用选择性外延生长(SEG)工艺制造半导体器件的方法。 一方面,该方法包括提供半导体衬底,在半导体衬底上形成绝缘材料的图案,由此限定被覆盖和非覆盖的表面,对具有绝缘的衬底的被覆盖和非覆盖表面进行清洁处理 定义的图案,将具有绝缘图案的衬底加载到外延反应器的反应室中,并开始选择性外延生长,其包括在外延反应室中可能具有至少一种第一载气的至少一种半导体源气体的注入 反应堆。 该方法还包括在选择性外延生长之前,通过注入含有卤素的蚀刻气体,可能在第二载气中,在反应室中将基板的表面进行原位预处理。

    Method for Manufacturing a Junction
    9.
    发明申请
    Method for Manufacturing a Junction 有权
    制造结点的方法

    公开(公告)号:US20100167446A1

    公开(公告)日:2010-07-01

    申请号:US12647773

    申请日:2009-12-28

    摘要: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.

    摘要翻译: 本发明涉及包含具有受控掺杂剂(浓度)分布的均质结或异质结的半导体器件及其制造方法。 因此,本发明的一个方面是一种用于制造接合部的方法,包括形成包含第一浓度的第一掺杂剂的第一半导体材料; 形成包含第二掺杂剂的第二半导体材料,其具有第二浓度从而形成结,并且通过原子层外延或气相掺杂使至少一部分适于在第一半导体材料上形成第二掺杂剂的前体单层的单层沉积 在形成第二半导体材料之前,从而增加第二掺杂剂在该结处的第二浓度。

    Method for Growing a Monocrystalline Tin-Containing Semiconductor Material
    10.
    发明申请
    Method for Growing a Monocrystalline Tin-Containing Semiconductor Material 审中-公开
    生产含单晶锡的半导体材料的方法

    公开(公告)号:US20140020619A1

    公开(公告)日:2014-01-23

    申请号:US14008560

    申请日:2012-03-29

    IPC分类号: H01L21/02

    摘要: Disclosed are methods for growing Sn-containing semiconductor materials. In some embodiments, an example method includes providing a substrate in a chemical vapor deposition (CVD) reactor, and providing a semiconductor material precursor, a Sn precursor, and a carrier gas in the CVD reactor. The method further includes epitaxially growing a Sn-containing semiconductor material on the substrate, where the Sn precursor comprises tin tetrachloride (SnCl4). The semiconductor material precursor may be, for example, digermane, trigermane, higher-order germanium precursors, or a combination thereof. Alternatively, the semiconductor material precursor may be a silicon precursor.

    摘要翻译: 公开了用于生长含Sn半导体材料的方法。 在一些实施例中,示例性方法包括在化学气相沉积(CVD)反应器中提供衬底,以及在CVD反应器中提供半导体材料前体,Sn前体和载气。 该方法还包括在衬底上外延生长含Sn半导体材料,其中Sn前体包括四氯化锡(SnCl 4)。 半导体材料前体可以是例如二摩尔,三面体,高级锗前体,或其组合。 或者,半导体材料前体可以是硅前体。