公开(公告)号：US06665843B2

公开(公告)日：2003-12-16

申请号：US10053197

申请日：2002-01-18

申请人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

发明人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.

公开(公告)号：US06535075B2

公开(公告)日：2003-03-18

申请号：US09737929

申请日：2000-12-15

申请人： Roland Frech ,  Erich Klink ,  Jochen Supper

发明人： Roland Frech ,  Erich Klink ,  Jochen Supper

IPC分类号： H03H701

CPC分类号： H01L27/0805

摘要： The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.

摘要翻译： 本发明涉及一种用于半导体芯片（10）的可调片上容量电路，该半导体芯片（10）安装在基板（30）上并且包括多个电源去耦电容器（20-23），该电源去耦电容器可通过接通而被选择性地激活或去激活 或关闭供电系统。 片上检测电路（32）确定片上电源网络的电路特定的负载/卸载频率，响应于检测电路的信号的片上控制装置（28,33）增加或减少 片上容量（CSD）通过选择性地激活或去激活电源去耦电容器（20-23）。 片外路径阻抗（LMC，RMC），片外容量（CM）和片上容量（CC），包括多个电源去耦电容器（20-23）和寄生片上容量（ CP）形成谐振回路（40），其可通过改变片上电源去耦电容器的总容量（CSD）来调节。 通过调谐去耦电容器的总容量（CSD），满足谐振回路（40）的谐振条件，在该谐振回路（40）的谐振条件下达到最小开关功率噪声和最小开关功耗。

公开(公告)号：US06424058B1

公开(公告)日：2002-07-23

申请号：US09672809

申请日：2000-09-28

申请人： Roland Frech ,  Erich Klink ,  Jochen Supper

发明人： Roland Frech ,  Erich Klink ,  Jochen Supper

IPC分类号： H02M306

CPC分类号： G01R27/2605 ,  G01R31/27 ,  Y10T307/74 ,  Y10T307/766 ,  Y10T307/826

摘要： The invention relates to a testable on-chip capacitor cell 10 including a decoupling capacitor (Ci) which can be disconnected from the power distribution network and discharged through a cell internal discharge circuit. An externally controllable switch (Si) connects in a first switching position the decoupling capacitor to the power supply system and disconnects in a second switching position the decoupling capacitor from the power supply system and connects it to a resistor (Ri) which is part of the discharge circuit. An off-chip control unit (16) is provided for toggling the switch with a frequency fT between its first and second position to perform a capacitor test operation. By a current measurement device the averaged power supply current demand of the decoupling capacitor is measured when switch (Si) is toggled. The actual capacity of the decoupling capacitor is determined as a function of the power supply voltage, of the switch toggling frequency (fT) and of the averaged power supply current measured. The invention also relates to a semiconductor chip containing a plurality of capacitors cells of the type described, and to a method for testing the power supply decoupling capacity of such chips.

摘要翻译： 本发明涉及一种可测试的片上电容器单元10，其包括可以从配电网络断开并通过单元内部放电电路放电的去耦电容器（Ci）。 外部可控开关（Si）将去耦电容器的第一开关位置连接到电源系统，并在去耦电容器与电源系统的第二开关位置断开，并将其连接到电阻器（Ri），该电阻器 放电电路。 提供了片外控制单元（16），用于在第一和第二位置之间以频率fT切换开关，以执行电容器测试操作。 通过电流测量装置，当开关（Si）被切换时，测量去耦电容器的平均电源电流需求。 去耦电容的实际容量根据电源电压，开关切换频率（fT）和测量的平均电源电流确定。 本发明还涉及包含所述类型的多个电容器单元的半导体芯片以及用于测试这种芯片的电源去耦能力的方法。

公开(公告)号：US06774836B2

公开(公告)日：2004-08-10

申请号：US10462529

申请日：2003-06-16

申请人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

发明人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

IPC分类号： H04L1702

CPC分类号： G05F1/46

摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.

摘要翻译： 一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。 为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案 最小化每个活动单位设备当定期运行时的当前需求。 选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动 在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

公开(公告)号：US20070109726A1

公开(公告)日：2007-05-17

申请号：US11281688

申请日：2005-11-17

申请人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren Becker ,  Bruce Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H02B1/00

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure wherein a) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, and b) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各个平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US07355125B2

公开(公告)日：2008-04-08

申请号：US11281688

申请日：2005-11-17

申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

IPC分类号： H05K1/03

CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.

摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

公开(公告)号：US08519720B2

公开(公告)日：2013-08-27

申请号：US13087602

申请日：2011-04-15

申请人： Roland Frech ,  Jochen Supper ,  Thomas-Michael Winkel

发明人： Roland Frech ,  Jochen Supper ,  Thomas-Michael Winkel

IPC分类号： G01R27/28

CPC分类号： G01R27/16 ,  G01R31/3004

摘要： A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).

摘要翻译： 一种用于确定电子系统内的预定负载位置处的电源阻抗分布（| Z（f）|）的方法。 在负载位置施加重复活动（如调制时钟树信号），并测量由该重复活动引起的局部电源电压（U（t））。 不是测量由重复活动引起的相应的电流消耗（I（t）），而是分析计算电流消耗。 本地电源阻抗曲线（| Z（f）|）被计算为测量的电源电压的频域电压和电流消耗量（| U（f）|，| I（f）|） （U（t））和计算出的电流消耗（I（t））。

公开(公告)号：US20120013353A1

公开(公告)日：2012-01-19

申请号：US13087602

申请日：2011-04-15

申请人： Roland Frech ,  Jochen Supper ,  Thomas-Michael Winkel

发明人： Roland Frech ,  Jochen Supper ,  Thomas-Michael Winkel

IPC分类号： G01R27/28

CPC分类号： G01R27/16 ,  G01R31/3004

摘要： A method for determining a power supply impedance profile (|Z(f)|) at a predetermined load location within an electronic system. A repetitive activity (such as a modulated clock tree signal) is applied in the load location, and the local power supply voltage (U(t)) caused by this repetitive activity is measured. Rather than measuring the corresponding current consumption (I(t)) caused by the repetitive activity, the current consumption is calculated analytically. The local power supply impedance profile (|Z(f)|) is calculated as the ratio of the frequency-domain voltage and current consumption magnitudes (|U(f)|, |I(f)|) of the measured power supply voltage (U(t)) and the calculated current consumption (I(t)).

摘要翻译： 一种用于确定电子系统内的预定负载位置处的电源阻抗分布（| Z（f）|）的方法。 在负载位置施加重复活动（如调制时钟树信号），并测量由该重复活动引起的局部电源电压（U（t））。 不是测量由重复活动引起的相应的电流消耗（I（t）），而是分析计算电流消耗。 本地电源阻抗曲线（| Z（f）|）被计算为测量的电源电压的频域电压和电流消耗量（| U（f）|，| I（f）|） （U（t））和计算出的电流消耗（I（t））。

公开(公告)号：US08659310B2

公开(公告)日：2014-02-25

申请号：US13087550

申请日：2011-04-15

申请人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

发明人： Martin Eckert ,  Roland Frech ,  Jochen Supper ,  Otto A. Torreiter

IPC分类号： G01R31/3187

CPC分类号： G01R31/31721 ,  G01R31/3004

摘要： A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).

摘要翻译： 一种用于对电子系统内的集成电路芯片进行电源质量自检的方法和系统。 电子系统受到明确的重复活动，例如通过使用调幅系统时钟树。 由于重复的活动导致芯片内的电流消耗，对于芯片上的位置测量时域本地电源电压（U（t））。 一组时域测量电压数据（U（t））被积累并变换到频域以产生局部电压分布（U（f））。 将本地电压曲线（U（f））与参考电压曲线（U0（f））进行比较，以验证被测芯片位置的电源质量是否足够。 或者，可以将从局部电压分布（U（f））估计的局部阻抗曲线Z（f）与参考阻抗曲线Z0（f）进行比较。

公开(公告)号：US09709625B2

公开(公告)日：2017-07-18

申请号：US13170512

申请日：2011-06-28

申请人： Martin Eckert ,  Roland Frech ,  Claudio Siviero ,  Jochen Supper ,  Otto A. Torreiter ,  Thomas-Michael Winkel

发明人： Martin Eckert ,  Roland Frech ,  Claudio Siviero ,  Jochen Supper ,  Otto A. Torreiter ,  Thomas-Michael Winkel

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185

CPC分类号： G01R31/2851 ,  G01R31/2879 ,  G01R31/3004 ,  G01R31/3012 ,  G01R31/318575

摘要： A method for determining power consumption of a power domain within an integrated circuit is presented. In a first step, a local power supply impedance profile (Z(f)) of this power domain is determined. Subsequently, a local time-resolved power supply voltage (U(t)) is measured while a well-defined periodic activity is executed in power domain. A set of time-domain measured voltage data (U(t)) is thus accumulated and transformed into the frequency domain to yield a voltage spectrum (U(f)). A current spectrum I(t) is calculated from this voltage profile (U(f)) by using the power supply impedance profile Z(f) of this power domain as I(t)=Ff−1{U(f)/Z(f)}. Finally, a time-resolved power consumption spectrum P(t) is determined from measured voltage spectrum U(t)) and calculated current spectrum (I(t)). This power consumption (P(t)) may be compared with a reference (Pref(t)) to verify whether power consumption within power domain matches expectations.