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    Method and system for quantifying the integrity of an on-chip power supply network
    1.
    发明授权
    Method and system for quantifying the integrity of an on-chip power supply network 失效

    公开(公告)号：US06665843B2

    公开(公告)日：2003-12-16

    申请号：US10053197

    申请日：2002-01-18

    申请人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    发明人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.

    Tunable on-chip capacity
    2.
    发明授权
    Tunable on-chip capacity 失效
    可调芯片容量

    公开(公告)号：US06535075B2

    公开(公告)日：2003-03-18

    申请号：US09737929

    申请日：2000-12-15

    申请人： Roland Frech ,  Erich Klink ,  Jochen Supper

    发明人： Roland Frech ,  Erich Klink ,  Jochen Supper

    IPC分类号： H03H701

    CPC分类号： H01L27/0805

    摘要： The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors. By tuning the total capacity (CSD) of the decoupling capacitors a resonance condition of the resonance loop (40) is met under which a minimum of switching power noise and a minimum switching power consumption is achieved.

    摘要翻译： 本发明涉及一种用于半导体芯片（10）的可调片上容量电路，该半导体芯片（10）安装在基板（30）上并且包括多个电源去耦电容器（20-23），该电源去耦电容器可通过接通而被选择性地激活或去激活 或关闭供电系统。 片上检测电路（32）确定片上电源网络的电路特定的负载/卸载频率，响应于检测电路的信号的片上控制装置（28,33）增加或减少 片上容量（CSD）通过选择性地激活或去激活电源去耦电容器（20-23）。 片外路径阻抗（LMC，RMC），片外容量（CM）和片上容量（CC），包括多个电源去耦电容器（20-23）和寄生片上容量（ CP）形成谐振回路（40），其可通过改变片上电源去耦电容器的总容量（CSD）来调节。 通过调谐去耦电容器的总容量（CSD），满足谐振回路（40）的谐振条件，在该谐振回路（40）的谐振条件下达到最小开关功率噪声和最小开关功耗。

    Testable on-chip capacity
    3.
    发明授权
    Testable on-chip capacity 失效
    片上容量可测

    公开(公告)号：US06424058B1

    公开(公告)日：2002-07-23

    申请号：US09672809

    申请日：2000-09-28

    申请人： Roland Frech ,  Erich Klink ,  Jochen Supper

    发明人： Roland Frech ,  Erich Klink ,  Jochen Supper

    IPC分类号： H02M306

    CPC分类号： G01R27/2605 ,  G01R31/27 ,  Y10T307/74 ,  Y10T307/766 ,  Y10T307/826

    摘要： The invention relates to a testable on-chip capacitor cell 10 including a decoupling capacitor (Ci) which can be disconnected from the power distribution network and discharged through a cell internal discharge circuit. An externally controllable switch (Si) connects in a first switching position the decoupling capacitor to the power supply system and disconnects in a second switching position the decoupling capacitor from the power supply system and connects it to a resistor (Ri) which is part of the discharge circuit. An off-chip control unit (16) is provided for toggling the switch with a frequency fT between its first and second position to perform a capacitor test operation. By a current measurement device the averaged power supply current demand of the decoupling capacitor is measured when switch (Si) is toggled. The actual capacity of the decoupling capacitor is determined as a function of the power supply voltage, of the switch toggling frequency (fT) and of the averaged power supply current measured. The invention also relates to a semiconductor chip containing a plurality of capacitors cells of the type described, and to a method for testing the power supply decoupling capacity of such chips.

    摘要翻译： 本发明涉及一种可测试的片上电容器单元10，其包括可以从配电网络断开并通过单元内部放电电路放电的去耦电容器（Ci）。 外部可控开关（Si）将去耦电容器的第一开关位置连接到电源系统，并在去耦电容器与电源系统的第二开关位置断开，并将其连接到电阻器（Ri），该电阻器 放电电路。 提供了片外控制单元（16），用于在第一和第二位置之间以频率fT切换开关，以执行电容器测试操作。 通过电流测量装置，当开关（Si）被切换时，测量去耦电容器的平均电源电流需求。 去耦电容的实际容量根据电源电压，开关切换频率（fT）和测量的平均电源电流确定。 本发明还涉及包含所述类型的多个电容器单元的半导体芯片以及用于测试这种芯片的电源去耦能力的方法。

    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules
    5.
    发明申请
    Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules 有权
    通过/ BSM模式优化，可以降低单个和多个芯片模块上的直流梯度和引脚电流密度

    公开(公告)号：US20070022398A1

    公开(公告)日：2007-01-25

    申请号：US11184350

    申请日：2005-07-19

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Thomas Strach ,  Jochen Supper

    IPC分类号： G06F17/50 ,  H01L21/00

    CPC分类号： H01L23/49833 ,  G06F17/5068 ,  H01L23/50 ,  H01L23/5385 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011

    摘要： A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e.g., the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

    摘要翻译： 通过将两个不同的电压域分配给载体的接触表面的两个分开的区域，同时为两个电压域提供公共电接地来设计诸如集成电路芯片的电子装置的载体。 集成电路芯片可以是具有额定工作电压的微处理器，并且两个电压域的不同电压都在标称工作电压的公差范围内，但是一个电压域与高功率密度区域 微处理器（例如，微处理器内核）并提供略高的电压。 较高的电源电压域优选地具有大于1的电压引脚与接地引脚的比率。

    System and method for automatic insertion of on-chip decoupling capacitors
    6.
    发明授权
    System and method for automatic insertion of on-chip decoupling capacitors 失效
    自动插入片上去耦电容的系统和方法

    公开(公告)号：US07302664B2

    公开(公告)日：2007-11-27

    申请号：US11054916

    申请日：2005-02-10

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

    摘要翻译： 提供一种用于自动插入片上去耦电容器的系统和方法。 利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。 该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。 此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。 根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。 以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

    System and method for automatic insertion of on-chip decoupling capacitors
    7.
    发明申请
    System and method for automatic insertion of on-chip decoupling capacitors 失效
    自动插入片上去耦电容的系统和方法

    公开(公告)号：US20060190892A1

    公开(公告)日：2006-08-24

    申请号：US11054916

    申请日：2005-02-10

    申请人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    发明人： Anand Haridass ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

    摘要翻译： 提供一种用于自动插入片上去耦电容器的系统和方法。 利用该系统和方法，将集成电路设计划分为单元，确定集成电路的每个单元的噪声分布。 该噪声分布可以使用多个不同的已知机构中的任何一个产生，并且通常导致为集成电路产生噪声映射。 此后，将映射函数应用于每个单元的噪声图，以确定集成电路的单元所需的电容。 根据每个电池所需的电容，可以识别必要的去耦电容以及插入这些去耦电容器的位置。 以类似的方式，可以基于每个单元所确定的所需电容从集成电路的单元去除去耦电容器。

    Method for delta-noise reduction
    8.
    发明授权
    Method for delta-noise reduction 失效
    减少降噪的方法

    公开(公告)号：US06774836B2

    公开(公告)日：2004-08-10

    申请号：US10462529

    申请日：2003-06-16

    申请人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

    发明人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

    IPC分类号： H04L1702

    CPC分类号： G05F1/46

    摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.

    摘要翻译： 一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。 为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案 最小化每个活动单位设备当定期运行时的当前需求。 选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动 在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。