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    Printed circuit board and chip module
    1.
    发明授权
    Printed circuit board and chip module 有权
    印刷电路板和芯片模块

    公开(公告)号：US07355125B2

    公开(公告)日：2008-04-08

    申请号：US11281688

    申请日：2005-11-17

    申请人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

    发明人： Wiren D. Becker ,  Bruce J. Chamberlin ,  Roland Frech ,  Andreas Huber ,  George Katopis ,  Erich Klink ,  Andreas Rebmann ,  Thomas-Michael Winkel

    IPC分类号： H05K1/03

    CPC分类号： H05K1/0262 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663

    摘要： The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes. In order to provide a printed circuit board having an improved signal return path for basically all relevant signal layers at transitions between card, connector, module and chip while still holding the cross-section structure simple, it is proposed to establish a layer structure whereina) a split voltage plane is located adjacent to one side of one of said reference planes and comprises conducting portions for all of said at least three different voltage levels in respective plane parts, andb) a signal layer being located adjacent to said reference planes.

    摘要翻译： 本发明涉及计算机硬件设计，特别是涉及一种印刷电路板，其中印刷电路板包括专用于提供诸如具有至少三个不同参考平面的集成电路的电路板部件的布线。 为了提供一种印刷电路板，其具有改进的信号返回路径，用于基本上在卡，连接器，模块和芯片之间的转变处的所有相关信号层，同时仍然保持横截面结构简单，因此建议建立层结构，其中 ）分裂电压平面位于所述参考平面中的一个的一侧附近，并且包括用于各平面部分中的所有所述至少三个不同电压电平的导电部分，以及b）位于所述参考平面附近的信号层。

    Method and Apparatus for Generating Synchronization Signals for Synchronizing Multiple Chips in a System
    9.
    发明申请
    Method and Apparatus for Generating Synchronization Signals for Synchronizing Multiple Chips in a System 失效
    用于同步系统中多个芯片同步信号的方法和装置

    公开(公告)号：US20110033017A1

    公开(公告)日：2011-02-10

    申请号：US12906658

    申请日：2010-10-18

    申请人： Charlie C. Hwang ,  Wiren D. Becker ,  Timothy G. McNamara ,  Ching-Lung Tong

    发明人： Charlie C. Hwang ,  Wiren D. Becker ,  Timothy G. McNamara ,  Ching-Lung Tong

    IPC分类号： H04L7/04

    CPC分类号： G06F1/10 ,  H03L7/06

    摘要： A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically. This invention resolves the uncertainty problem and allows the synchronization signals to be generated deterministically independent of the chip global clock cycle time.

    摘要翻译： 一种用于产生多芯片系统的同步信号的时钟发生器电路。 时钟发生器电路包括从参考时钟和具有边缘检测逻辑的芯片全局时钟产生同步信号。 在具有多个芯片的高性能服务器系统设计中，服务器系统的常见做法是使用反馈时钟和延迟参考时钟来生成同步信号。 所产生的同步信号被传送到由全局时钟计时的锁存器，以用于芯片同步功能。 随着系统时钟频率被推高，由反馈时钟所产生的所生成的同步信号与由全局时钟计时的接收锁存器之间的相位差成为这个信号不能被确定地传送的循环时间的大部分。 本发明解决了不确定性问题，并允许确定地产生同步信号，而不依赖于芯片全局时钟周期时间。