公开(公告)号：US4841485A

公开(公告)日：1989-06-20

申请号：US116818

申请日：1987-11-05

申请人： Ronald J. Prilik ,  James R. Varner

发明人： Ronald J. Prilik ,  James R. Varner

IPC分类号： G11C29/00 ,  G11C7/20 ,  G11C11/41 ,  G11C11/413 ,  G11C29/34 ,  G11C29/36

CPC分类号： G11C7/20 ,  G11C29/36

摘要： A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.

公开(公告)号：US6058496A

公开(公告)日：2000-05-02

申请号：US955442

申请日：1997-10-21

申请人： Pamela Sue Gillis ,  Kevin William McCauley ,  Ronald J. Prilik ,  Donald Lawrence Wheater ,  Francis Woytowich, Jr.

发明人： Pamela Sue Gillis ,  Kevin William McCauley ,  Ronald J. Prilik ,  Donald Lawrence Wheater ,  Francis Woytowich, Jr.

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/317

摘要： A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

摘要翻译： 用于测试半导体芯片的方法和装置包括为半导体芯片提供公共输入/输出（I / O）或双向I / O焊盘。 I / O焊盘电耦合到片外驱动器（OCD）和芯片外接收器（OCR）。 OCD，I / O焊盘和OCR组合在通用输入/输出（CIO）或双向I / O配置中。 I / O焊盘由外部测试仪有效地断开，测试连接到开路焊盘的IO电路的性能参数。

公开(公告)号：US4928061A

公开(公告)日：1990-05-22

申请号：US330293

申请日：1989-03-29

申请人： Michael S. Dampier ,  Ronald J. Prilik ,  Norman R. Rapoport

发明人： Michael S. Dampier ,  Ronald J. Prilik ,  Norman R. Rapoport

IPC分类号： H05K3/46 ,  G01R31/26 ,  G01R31/28 ,  H05K1/00 ,  H05K1/11 ,  H05K3/40

CPC分类号： G01R31/2886 ,  H05K1/0298 ,  H05K1/117 ,  H05K3/403

摘要： A printed circuit board especially for use in device testing apparatus is provided. The circuit board includes a plurality of stacked layers of dielectric or insulating material with each of the layers having coated on one surface thereof a layer of conducting material defining a plane. The conducting material extends to at least one outer edge of the stack of the material for each plane and at each plane it is spaced with respect to the outer edge locations of all of the other planes. A plurality of lands extend vertically along the stack of material, each land while extending the entire length, only contacting the plane of conducting material extending to the edge at the location of the land whereby a signal applied to any given land is conducted only on the planes where that plane extends to the surface. The configuration for a testing device preferably is an annular configuration and the planes of conducting material extend to both the inner and outer surfaces and signals are applied to the outer surface from an external source and delivered to the test piece from the inner surface.

公开(公告)号：US5912901A

公开(公告)日：1999-06-15

申请号：US823446

申请日：1997-03-24

申请人： R. Dean Adams ,  Michael R. Ouellette ,  Ronald J. Prilik

发明人： R. Dean Adams ,  Michael R. Ouellette ,  Ronald J. Prilik

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/22 ,  G11C29/12

CPC分类号： G01R31/318555 ,  G01R31/2884 ,  G01R31/319

摘要： A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.

摘要翻译： 公开了一种用于测试集成电路的内置自检（BIST）装置和方法，其能够捕获所选故障的故障数据。 BIST装置包括产生至少第一时钟信号的时钟发生器和内置自测试器，其响应于第一时钟信号将预定的输入数据模式应用于集成电路。 此外，BIST装置包括用于将从集成电路接收的输出数据与预期输出数据进行比较的数据比较器。 当从集成电路接收的输出数据与预期输出数据不同时，数据比较器检测集成电路内的故障。 BIST装置还包括时钟控制器，其响应于所选择的故障发生的检测而禁用第一时钟信号。 通过在所选择的故障发生时能够对要停止的集成电路进行测试，增强了集成电路的故障分析。

公开(公告)号：US4686462A

公开(公告)日：1987-08-11

申请号：US780533

申请日：1985-09-26

申请人： Ronald J. Prilik

发明人： Ronald J. Prilik

IPC分类号： G01R31/26 ,  B23H7/04 ,  G01R31/319 ,  G01R15/12 ,  G06G7/12 ,  H03K5/153

CPC分类号： G01R31/31924 ,  B23H7/04

摘要： A tester for logic circuits provided with a fast recovery power supply for supplying high current to a logic circuit under test and for measuring a low current of the circuit under test. The power supply of the tester has first and second amplifiers coupled to the CMOS circuit being tested and having dual feedback loops with one loop controlling the resistance of the other loop. The first amplifier is coupled between a reference voltage and a capacitor supplying current to the CMOS circuit under test. The second amplifier is coupled between the same reference voltage, and the output of the first amplifier. A resistive feedback is coupled between the circuit under test and the output of the first amplifier and an AC coupled impedance switching means is coupled between the output of the second amplifier and across the resistive feedback whereby the impedance switch can alter the impedance of the resistive feedback by shunting the resistor to recharge the capacitor supplying current to the circuit under test.

摘要翻译： 具有用于向被测逻辑电路提供高电流并用于测量被测电路的低电流的快速恢复电源的逻辑电路的测试器。 测试器的电源具有耦合到正被测试的CMOS电路的第一和第二放大器，并且具有双反馈回路，其中一个回路控制另一个回路的电阻。 第一放大器耦合在参考电压和向正在测试的CMOS电路提供电流的电容器之间。 第二放大器耦合在相同的参考电压和第一放大器的输出之间。 电阻反馈耦合在被测电路之间，并且第一放大器和AC耦合阻抗开关装置的输出耦合在第二放大器的输出端和电阻反馈之间，由此阻抗开关可以改变电阻反馈的阻抗 通过分流电阻器为向被测电路提供电流的电容器充电。