公开(公告)号：US07271613B1

公开(公告)日：2007-09-18

申请号：US11070347

申请日：2005-03-02

申请人： Ross Voigt La Fetra ,  Rohit Kumar ,  Sai V. Vishwanthaiah

发明人： Ross Voigt La Fetra ,  Rohit Kumar ,  Sai V. Vishwanthaiah

IPC分类号： H03R19/0185

CPC分类号： G01D3/02

摘要： An integrated circuit includes at least a first and second compensation circuit that compensate for process, temperature, and other variable conditions that affect circuit performance. A compensation select circuit is coupled to selectively enable each of the first and second compensation circuits at respective first and second time periods to control a voltage on the input/output terminal to substantially equal a reference voltage and thereby determine appropriate compensation setting.

摘要翻译： 集成电路至少包括补偿电路性能的过程，温度和其他可变条件的第一和第二补偿电路。 耦合补偿选择电路以选择性地使第一和第二补偿电路中的每一个在相应的第一和第二时间周期上控制输入/输出端子上的电压基本上等于参考电压，从而确定适当的补偿设置。

公开(公告)号：US20200211531A1

公开(公告)日：2020-07-02

申请号：US16235776

申请日：2018-12-28

申请人： Rohit Kumar ,  Henrik Lindström ,  Henriette Cramer ,  Sarah Mennicken ,  Sravana Reddy ,  Jennifer Thom-Santelli

发明人： Rohit Kumar ,  Henrik Lindström ,  Henriette Cramer ,  Sarah Mennicken ,  Sravana Reddy ,  Jennifer Thom-Santelli

IPC分类号： G10L13/04 ,  G06F16/683

摘要： A text-to-speech engine creates audio output that includes synthesized speech and one or more media content item snippets. The input text is obtained and partitioned into text sets. A track having lyrics that match a part of one of the text sets is identified. The location of the track's audio that contains the lyric is extracted based on forced alignment data. The extracted audio is combined with synthesized speech corresponding to the remainder of the input text to form audio output.

公开(公告)号：US20080034378A1

公开(公告)日：2008-02-07

申请号：US11756678

申请日：2007-06-01

申请人： Rohit Kumar ,  Emerson Fang

发明人： Rohit Kumar ,  Emerson Fang

IPC分类号： G06F13/38

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： A driver circuit that consumes less current than other driver circuits combines a current-mode driver circuit with a voltage-mode driver circuit to provide impedance matching and signal equalization operations. In at least one embodiment of the invention, an apparatus includes a differential node and a driver circuit configured to generate a signal on the differential node. The driver circuit includes a first circuit portion configured to generate a first signal on the differential node based, at least in part, on a data signal. The first signal has a voltage swing based, at least in part, on a voltage on a power supply node. The driver circuit includes at least a second circuit portion configured to generate a current through the differential node based, at least in part, on a first bit-time of the data signal and an equalization operation, thereby adjusting the voltage swing of the signal.

摘要翻译： 与其他驱动电路相比，消耗更少电流的驱动电路将电流模式驱动电路与电压模式驱动电路相结合，提供阻抗匹配和信号均衡操作。 在本发明的至少一个实施例中，装置包括差分节点和被配置为在差分节点上产生信号的驱动器电路。 驱动器电路包括第一电路部分，其被配置为至少部分地基于数据信号来产生差分节点上的第一信号。 第一信号至少部分地基于电源节点上的电压进行电压摆幅。 驱动器电路至少包括第二电路部分，其被配置为至少部分地基于数据信号的第一比特时间和均衡操作来产生通过差分节点的电流，由此调整信号的电压摆幅。

公开(公告)号：US07227382B1

公开(公告)日：2007-06-05

申请号：US11048440

申请日：2005-02-01

申请人： Gerald R. Talbot ,  Rohit Kumar ,  Stephen C. Hale

发明人： Gerald R. Talbot ,  Rohit Kumar ,  Stephen C. Hale

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005 ,  H04L25/0278

摘要： A driver circuit. In one embodiment, the driver circuit includes a plurality of pull-up circuits and a plurality of pull-down circuits. The driver circuit also includes control logic that is coupled to activate/deactivate the pull-up and pull-down circuits. The driver circuit may perform emphasized signal transmissions having a voltage swing of a first magnitude or de-emphasized signal transmissions having a voltage swing of a second magnitude, wherein the first magnitude is greater than the second magnitude. The control logic is further configured to activate and/or deactivate pull-up and/or pull-down circuits such that the driver circuit output impedance in the emphasized mode is substantially equal to the output impedance in the de-emphasized mode.

摘要翻译： 驱动电路。 在一个实施例中，驱动器电路包括多个上拉电路和多个下拉电路。 驱动器电路还包括耦合以激活/去激活上拉和下拉电路的控制逻辑。 驱动器电路可以执行具有第一幅度的电压摆幅或具有第二幅度的电压摆幅的去加重信号传输的强调信号传输，其中第一幅度大于第二幅度。 控制逻辑还被配置为激活和/或去激活上拉和/或下拉电路，使得强调模式下的驱动电路输出阻抗基本上等于去加重模式中的输出阻抗。

公开(公告)号：US08915744B2

公开(公告)日：2014-12-23

申请号：US12776400

申请日：2010-05-09

申请人： Raman Srinivasan ,  Priyadharshini Sridhar ,  Swarna Srinivasan ,  Rohit Kumar ,  Radhika Jayapaul ,  Radhika Ganesan ,  Amit Nath ,  Vikash Agarwal

发明人： Raman Srinivasan ,  Priyadharshini Sridhar ,  Swarna Srinivasan ,  Rohit Kumar ,  Radhika Jayapaul ,  Radhika Ganesan ,  Amit Nath ,  Vikash Agarwal

IPC分类号： G09B3/00 ,  G09B7/00

CPC分类号： G09B7/00

摘要： The present invention relates to a system used for competency assessment of candidates. More particularly the present invention relates to an automated system for talent acquisition in an enterprise to identify talented candidates who meet the qualification standards specified by enterprise using a secured and light weight method of providing content including questions and responses in a distributed architecture. The data center server of the system may connect to Knowledge center server to receive the secure test content. The test content is transferred to one or more exam center servers from the data center server. The exam center servers assess the competency of candidates connected to them via candidate console devices (computational devices), by generating unique and standardized test content for each candidate. The system enables less effort, time and consequently money, that multiple test administrators may spend traveling to different test locations to support the system infrastructure.

摘要翻译： 本发明涉及一种用于候选人的能力评估的系统。 更具体地说，本发明涉及一种用于企业中人才获取的自动化系统，以使用在分布式架构中提供包括问题和响应的内容的安全轻量级方法来识别满足企业规定的资格标准的有才能的候选人。 系统的数据中心服务器可以连接到知识中心服务器，以接收安全的测试内容。 测试内容从数据中心服务器传输到一个或多个考试中心服务器。 考试中心服务器通过候选控制台设备（计算设备）评估与他们相关的候选人的能力，为每个候选人生成独特和标准化的测试内容。 该系统能够减少多个测试管理员花费的时间和时间，从而节省资金，以便支持系统基础设施。

公开(公告)号：US08503597B2

公开(公告)日：2013-08-06

申请号：US12982854

申请日：2010-12-30

申请人： Dennis M. Fischette ,  Rohit Kumar

发明人： Dennis M. Fischette ,  Rohit Kumar

IPC分类号： H03D3/24

CPC分类号： H03D3/24 ,  H03L7/1075 ,  H03L2207/06

摘要： A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.

摘要翻译： 一种减少双路锁相环（PLL）锁定时间的方法和机制。 PLL包括双通道低通滤波器（LPF）。 LPF包括第一过滤器和第二过滤器。 第一滤波器包括无源二阶超前延迟低通滤波器。 第二滤波器包括一阶滞后低通滤波器。 在锁定获取状态期间，旁路第二级中的阻抗值，这增加了PLL的环路带宽。 此外，增加第一级内的电阻以增加第一级的增益并保持PLL内的稳定性。 在锁定状态期间，阻抗值可能不再被旁路，并且增加的电阻可能返回到其原始值。

公开(公告)号：US20130084554A1

公开(公告)日：2013-04-04

申请号：US13426578

申请日：2012-03-21

申请人： Viral Prakash SHAH ,  Nawaz Shaikh ,  Rohit Kumar

发明人： Viral Prakash SHAH ,  Nawaz Shaikh ,  Rohit Kumar

IPC分类号： G09B7/00

CPC分类号： G09B7/02

摘要： The present subject matter relates to a method for customized question paper generation. The method includes assigning at least one key value to each of a plurality of questions, and storing the questions along with the at least one associated key value in a question bank. The method further includes fetching the stored questions based on rules in a question paper template, where the rules are based on the at least one key value. Furthermore, the method includes validating the fetched questions based on at least one constraint and generating the question paper based on the validating.

摘要翻译： 本主题涉及用于定制问题纸生成的方法。 该方法包括将至少一个键值分配给多个问题中的每一个，并将问题与至少一个相关联的键值一起存储在问题库中。 该方法还包括基于问题纸模板中的规则获取存储的问题，其中规则基于至少一个键值。 此外，该方法包括基于至少一个约束来验证所提取的问题，并且基于验证生成问题文件。

公开(公告)号：US07256636B2

公开(公告)日：2007-08-14

申请号：US11240231

申请日：2005-09-30

申请人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

发明人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

IPC分类号： H03H11/26

CPC分类号： H03L7/0812

摘要： A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

公开(公告)号：US20070075757A1

公开(公告)日：2007-04-05

申请号：US11240231

申请日：2005-09-30

申请人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

发明人： Rohit Kumar ,  Anand Daga ,  Sanjay Sethi

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A voltage controlled delay line (VCDL). The VCDL includes one or more cells. Each of the one or more cells includes two or more inputs and an output. Each of the one or more cells is configured to provide a delay as well as an interpolation function and a multiplexer function. The VCDL may be used to provide delay in a delay locked loop (DLL).

摘要翻译： 电压控制延时线（VCDL）。 VCDL包括一个或多个单元。 一个或多个单元中的每个单元包括两个或更多个输入和输出。 一个或多个单元中的每一个被配置为提供延迟以及内插函数和多路复用器功能。 VCDL可用于在延迟锁定环（DLL）中提供延迟。

公开(公告)号：US08570881B2

公开(公告)日：2013-10-29

申请号：US11668010

申请日：2007-01-29

申请人： Gerald R. Talbot ,  Paul C. Miranda ,  Emerson S. Fang ,  Rohit Kumar

发明人： Gerald R. Talbot ,  Paul C. Miranda ,  Emerson S. Fang ,  Rohit Kumar

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/08 ,  H04J1/16 ,  H04J3/14 ,  G01R31/316 ,  G01R31/317 ,  H04L1/20

CPC分类号： G01R31/30 ,  G01R31/3004 ,  G01R31/316 ,  G01R31/317 ,  H04L1/20 ,  H04L7/0337

摘要： A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

摘要翻译： 用于表征通信接口的技术包括基于由接口的接收机的采样设备采样的数据来确定接口的电压余量和定时裕度。 在本发明的至少一个实施例中，用于确定与集成电路的接收机电路相关联的裕量的方法包括由接收机电路的接收机采样电路在一段时间周期性地对信号进行采样以产生信号的采样版本。 该方法包括递增地改变与信号相关联的参数的值。 参数的变化是通过该时间段内参数值的范围。 该方法包括至少部分地基于信号的采样版本来确定与参数相关联的接收机电路的边缘值。