摘要:
Described herein are technologies related to an implementation of a divider-less digital phase-locked loop (DPLL) that includes a loop response matching a higher order sigma delta.
摘要:
Some demonstrative embodiments include devices, systems and/or methods of wireless communication over a plurality of wireless communication frequency channels. For example, a wireless communication device may include a frequency source to generate a source frequency signal; a plurality of local-oscillator (LO) generators to generate a respective plurality of different carrier signal frequencies based on the source frequency signal; and a plurality of radio-frequency (RF) paths to simultaneously communicate over the plurality of carrier signal frequencies, respectively.
摘要:
Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of out-put signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.
摘要:
Some demonstrative embodiments include devices, systems and/or methods of wireless communication over a plurality of wireless communication frequency channels. For example, a wireless communication device may include a frequency source to generate a source frequency signal; a plurality of local-oscillator (LO) generators to generate a respective plurality of different carrier signal frequencies based on the source frequency signal; and a plurality of radio-frequency (RF) paths to simultaneously communicate over the plurality of carrier signal frequencies, respectively.
摘要:
Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.
摘要:
Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.
摘要:
Some demonstrative embodiments include devices, systems and/or methods of configurable frequency signal generation. For example, a device may include at least one configurable local-oscillator (LO) generator to receive an input frequency signal and one or more configurable input values and to convert the input frequency signal into at least one output frequency signal according to a configurable conversion ratio, which is based on the configurable input values.
摘要:
Embodiments provide a voltage controlled oscillator (VCO) having reduced single-ended capacitance. In one embodiment, the VCO may include a transformer, a capacitor bank, and a gain stage. The transformer may include a primary inductor and a secondary inductor, and the secondary inductor may be inductively coupled to the primary inductor. The capacitor bank may be coupled to the secondary inductor and may provide a majority of a total capacitance of the VCO. The gain stage may be coupled to the primary inductor and configured to receive a supply signal and to drive a differential current in the primary inductor, thereby inducing an output signal across the secondary inductor having a frequency equal to a resonant frequency of the VCO.
摘要:
Some demonstrative embodiments include devices, systems and/or methods of configurable frequency signal generation. For example, a device may include at least one configurable local-oscillator (LO) generator to receive an input frequency signal and one or more configurable input values and to convert the input frequency signal into at least one output frequency signal according to a configurable conversion ratio, which is based on the configurable input values.
摘要:
This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.