公开(公告)号：US20120215965A1

公开(公告)日：2012-08-23

申请号：US13372800

申请日：2012-02-14

申请人： Ryoichi Inada ,  Ryo Fujita ,  Takuma Nishimura ,  Koji Matsuda

发明人： Ryoichi Inada ,  Ryo Fujita ,  Takuma Nishimura ,  Koji Matsuda

IPC分类号： G06F12/10 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F12/1027 ,  G06F2212/7201

摘要： A nonvolatile memory stores therein a plurality of partitioned translation tables which are created by partitioning a logical-to-physical address translation table in a page unit. A RAM stores therein a logical-to-physical address translation table cache for storing at least the one or more partitioned translation tables, a translation-table management table for managing the partitioned translation tables, and a cache management table for managing the logical-to-physical address translation table cache. The translation-table management table includes a cache presence-or-absence flag and a cache entry number, the cache presence-or-absence flag being used for indicating that the partitioned translation tables are stored into the logical-to-physical address translation table cache, the cache entry number being used for indicating storage destinations of the partitioned translation tables in the logical-to-physical address translation table cache. Reading/writing processings of information in the logical-to-physical address translation table between the nonvolatile memory and the RAM are performed in the page unit.

摘要翻译： 非易失性存储器中存储有通过在页面单元中划分逻辑到物理地址转换表而创建的多个分区转换表。 RAM中存储有至少存储一个或多个分区转换表的逻辑到物理地址转换表缓存，用于管理分区转换表的转换表管理表，以及用于管理逻辑到 物理地址转换表缓存。 翻译表管理表包括高速缓存存在或不存在标志和高速缓存条目号，高速缓存存在或不存在标志用于指示分区转换表被存储到逻辑到物理地址转换表中 高速缓存，用于指示逻辑到物理地址转换表缓存中的分区转换表的存储目的地的高速缓存条目号。 在页面单元中执行在非易失性存储器和RAM之间的逻辑到物理地址转换表中的信息的读/写处理。

公开(公告)号：US08949515B2

公开(公告)日：2015-02-03

申请号：US13512958

申请日：2010-12-01

申请人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

发明人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (2), physical blocks are classified into three types: scratch blocks (22), data blocks (23), and erased blocks (24). Data writing from a host device (3) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

摘要翻译： 公开了一种使用非易失性半导体存储器的存储装置，其实现了该装置的高性能和长寿命。 当管理非易失性半导体存储器（2）时，物理块被分为三种类型：暂存块（22），数据块（23）和擦除块（24）。 在暂存块上执行来自主机（3）的数据写入。 当暂存块内的空页数少于预定数量或不再存在时，该块被当作数据块处理，并且其中一个擦除块被新分配为暂存块。 如果擦除块不足，则从数据块中选择具有相对较少有效数据的块。 将块中包含的所有有效数据复制到暂存块后，块被擦除，从而获取被擦除的块。

公开(公告)号：US20120246399A1

公开(公告)日：2012-09-27

申请号：US13512958

申请日：2010-12-01

申请人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

发明人： Masataka Nishi ,  Ryo Fujita ,  Ryoichi Inada ,  Takuma Nishimura ,  Masahiro Shiraishi ,  Koji Matsuda

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7203

摘要： Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (2), physical blocks are classified into three types: scratch blocks (22), data blocks (23), and erased blocks (24). Data writing from a host device (3) is performed on the scratch blocks. When the number of empty pages within a scratch block becomes less than a predetermined number or no longer exists, the block is treated thereafter as a data block, and one of the erased blocks is newly assigned as a scratch block. If there are insufficient erased blocks, a block with relatively less valid data is selected from among the data blocks. After copying all valid data included in the block to a scratch block, the block is erased, and thus an erased block is acquired.

摘要翻译： 公开了一种使用非易失性半导体存储器的存储装置，其实现了该装置的高性能和长寿命。 当管理非易失性半导体存储器（2）时，物理块被分为三种类型：暂存块（22），数据块（23）和擦除块（24）。 在暂存块上执行来自主机（3）的数据写入。 当暂存块内的空页数少于预定数量或不再存在时，该块被当作数据块处理，并且其中一个擦除块被新分配为暂存块。 如果擦除块不足，则从数据块中选择具有相对较少有效数据的块。 将块中包含的所有有效数据复制到暂存块后，块被擦除，从而获取被擦除的块。

公开(公告)号：US06762976B1

公开(公告)日：2004-07-13

申请号：US09674086

申请日：2000-10-26

申请人： Katsuaki Tamaru ,  Ryo Fujita ,  Susumu Tosaka

发明人： Katsuaki Tamaru ,  Ryo Fujita ,  Susumu Tosaka

IPC分类号： G04B3700

CPC分类号： G04B43/002 ,  G04B37/005 ,  G04B37/055

摘要： There is disposed a middle comprising a metallic inner middle (20) in which a movement (30) is housed, and a metallic outer middle (21) covering at least a part of the inner middle, and an elastic shock absorber (35) disposed between the inner middle and the outer middle.

摘要翻译： 设置有包括容纳运动（30）的金属内部中间（20）的中部和覆盖内部中间部分的至少一部分的金属外部中间（21）和设置在弹性减震器（35） 在中间和中部之间。

公开(公告)号：US06609232B2

公开(公告)日：2003-08-19

申请号：US09791818

申请日：2001-02-26

申请人： Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

发明人： Teppei Hirotsu ,  Ryo Fujita ,  Kotaro Shimamura ,  Hiromichi Yamada ,  Dai Fujii ,  Haruyuki Nakayama

IPC分类号： G06F945

CPC分类号： G06F17/505

摘要： In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

摘要翻译： 在子块间路径的逻辑复合中，生成包括所有子块间路径的电路。 对所生成的电路进行逻辑复合以实现子块间路径的逻辑复合。 通过将子块间路径视为子块内路径，对于子块间路径的逻辑组合不需要输入/输出延迟限制。 这使得可以充分利用逻辑复合工具的性能，因此可以通过处理的一个操作来优化子块间路径。

公开(公告)号：US5900917A

公开(公告)日：1999-05-04

申请号：US903259

申请日：1997-07-25

申请人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

发明人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

IPC分类号： G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/262 ,  H04N7/26 ,  H04N7/50 ,  H04N5/445

CPC分类号： G09G5/39 ,  G06T1/20 ,  H04N19/42 ,  H04N19/61 ,  H04N5/2624 ,  G09G2340/125 ,  G09G2360/123 ,  G09G5/36 ,  G09G5/399

摘要： An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input section, a video output section, a controller for selecting connection of each element to the video input or output section, and an image drawing section for reading and writing video data from and in the elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover the numbers of the elements respectively connected to the video input and output sections can be adaptively varied.

摘要翻译： 图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和 从元素中写入视频数据。 存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

公开(公告)号：US5801706A

公开(公告)日：1998-09-01

申请号：US425514

申请日：1995-04-20

申请人： Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

发明人： Ryo Fujita ,  Mitsuru Soga ,  Yasushi Fukunaga ,  Takehiko Nishida

IPC分类号： G09G5/397 ,  G06T1/60 ,  G06T11/00 ,  G06T15/00 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399

CPC分类号： G06T15/005 ,  G06T1/60 ,  G09G5/393 ,  G09G5/395

摘要： A three-dimensional graphic display apparatus performs hidden surface removal and color blending. Particularly, the graphic display apparatus includes a configuration of a special purpose memory for graphics, thereby forming a configuration of a graphic display apparatus using the special purpose memory. The special purpose memory for graphics includes a memory cell holding intensity information (RGB) and window information about each pixel, an XY coordinate converter converting XY coordinates of a pixel to be written to a memory address, an intensity blending processor, and hidden-surface removal and window comparators, all of which are formed on the same chip.

摘要翻译： 三维图形显示装置执行隐藏的表面去除和颜色混合。 特别地，图形显示装置包括用于图形的专用存储器的配置，从而形成使用专用存储器的图形显示装置的配置。 用于图形的专用存储器包括存储单元保持强度信息（RGB）和关于每个像素的窗口信息，XY坐标转换器将要写入的像素的XY坐标转换到存储器地址，强度混合处理器和隐藏表面 去除和窗口比较器，它们都在同一个芯片上形成。

公开(公告)号：US5204945A

公开(公告)日：1993-04-20

申请号：US609615

申请日：1990-11-06

申请人： Toru Sakaibara ,  Hideyuki Hara ,  Ryo Fujita

发明人： Toru Sakaibara ,  Hideyuki Hara ,  Ryo Fujita

IPC分类号： G06T11/00 ,  G06T11/20 ,  G09G5/20

CPC分类号： G09G5/20

摘要： The display system and a thick line display method realizes a high-speed and accurate display of a thick line without any disorder even if a display range is to be processed by two or more clip frames when the thick line is to be displayed by parallel setting a reference line component and at least one additional line component which is obtained by parallel moving the reference line component in a display system such as an information processing unit that displays graphs. For this purpose, a clip frame showing a display range is expanded by a predetermined width equal to or larger than the total width of additional line components to be set at least at one side of the reference line component and the additional line component is obtained in that expanded frame, and the line component within the clip frame of the additional line component and the reference line component within the clip frame are displayed.

摘要翻译： 显示系统和粗线显示方法即使在通过平行设置来显示粗线时，通过两个或更多个夹子帧来处理显示范围也可以实现粗线的高速和精确的显示， 参考线组件和至少一个附加线组件，其通过在诸如显示图形的信息处理单元等显示系统中平行移动参考线组件而获得。 为此目的，示出显示范围的剪辑框架被扩展预定宽度，该预定宽度等于或大于要设置在参考线路部件的一侧的附加线路分量的总宽度，并且获得附加线路分量 显示该扩展帧以及附加线分量的剪辑帧内的线分量和剪辑帧内的参考线分量。

公开(公告)号：US08008622B2

公开(公告)日：2011-08-30

申请号：US12630346

申请日：2009-12-03

申请人： Ryo Fujita ,  Haruo Yoda ,  Kimiaki Ando ,  Yuji Inoue ,  Masato Muraki

发明人： Ryo Fujita ,  Haruo Yoda ,  Kimiaki Ando ,  Yuji Inoue ,  Masato Muraki

IPC分类号： H01J37/26

CPC分类号： H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J2237/31762 ,  H01J2237/31769

摘要： High-contrast exposure is performed by use of a small dose of electron beams, a pattern is formed on a wafer with high accuracy, and high-precision inspection is performed. In pattern formation, proximity effect correction processing is performed. Moreover, exposure of electron beams is performed based on a result of filtering using an inverse characteristic of exposure characteristics of the electron beams. Furthermore, in pattern inspection, electron beams are irradiated based on a result of filtering for obtaining a peripheral region of an edge of the pattern formed.

摘要翻译： 通过使用小剂量的电子束进行高对比度曝光，以高精度在晶片上形成图案，进行高精度检查。 在图案形成中，执行邻近效应校正处理。 此外，基于使用电子束的曝光特性的逆特性的滤波结果来执行电子束的曝光。 此外，在图案检查中，基于滤波结果照射电子束，以获得形成的图案的边缘的周边区域。

公开(公告)号：US20060203000A1

公开(公告)日：2006-09-14

申请号：US11365493

申请日：2006-03-02

申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

IPC分类号： G09G5/39

CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

摘要： A data processing system including: a memory controller; and a memory connected to said memory controller; wherein said memory controller includes a rendering circuit thereby to execute a rendering command generating display data based on graphic data provided after processing a program in a CPU, and stores said display data in said memory.