公开(公告)号：US20110062539A1

公开(公告)日：2011-03-17

申请号：US12885093

申请日：2010-09-17

申请人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

发明人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

IPC分类号： H01L29/82 ,  H01L21/04

CPC分类号： H01L27/228 ,  B82Y25/00 ,  H01F10/131 ,  H01F10/14 ,  H01F10/142 ,  H01F10/145 ,  H01F10/20 ,  H01F10/22 ,  H01F10/3254 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76844 ,  H01L27/105 ,  H01L43/08 ,  H01L43/12

摘要： To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.

摘要翻译： 提供抑制重写特性劣化的半导体器件。 在存储单元区域中，半导体磁存储器件中的磁阻元件形成为阵列形状，其方式是将磁阻元件布置在沿一个方向延伸的数字线与沿大致垂直于 数字线。 数字线和位线具有这样一种布线结构，其通过用覆盖层覆盖作为布线主体的铜膜而构成。 磁阻元件的一端侧经由由非磁性材料形成的顶部通孔电耦合到位线。

公开(公告)号：US20110121419A1

公开(公告)日：2011-05-26

申请号：US13021079

申请日：2011-02-04

申请人： Shuichi UENO ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

发明人： Shuichi UENO ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

摘要翻译： 一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。

公开(公告)号：US07906346B2

公开(公告)日：2011-03-15

申请号：US12187846

申请日：2008-08-07

申请人： Shuichi Ueno ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

发明人： Shuichi Ueno ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

摘要翻译： 一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。

公开(公告)号：US20090039451A1

公开(公告)日：2009-02-12

申请号：US12187846

申请日：2008-08-07

申请人： Shuichi UENO ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

发明人： Shuichi UENO ,  Haruo Furuta ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Shin Hasegawa ,  Shinya Hirano ,  Hiroyuki Chibahara ,  Hiroshi Oshita

IPC分类号： H01L29/82 ,  H01L23/52 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A method for manufacturing a magnetic memory device which includes a TMR element, and the method includes: a step of forming a lower wiring layer; a step of forming an interlayer insulating layer on the lower wiring layer; a step of forming an opening in the interlayer insulating layer so that the lower wiring layer is exposed; a step of forming a barrier metal layer so that the interlayer insulating layer and an inner surface of the opening are covered; a step of forming a metal layer on the barrier metal layer so that the opening is embedded; a polishing step of removing the metal layer on the barrier metal layer through polishing using the barrier metal layer as a stopper so that a wiring layer that includes a metal layer being embedded in the opening and the barrier metal layer is formed; and an element fabricating step of fabricating a TMR element on the wiring layer.

摘要翻译： 一种制造包括TMR元件的磁存储器件的方法，所述方法包括：形成下布线层的步骤; 在下布线层上形成层间绝缘层的步骤; 在所述层间绝缘层中形成开口以使所述下部布线层露出的步骤; 形成阻挡金属层以使得层间绝缘层和开口的内表面被覆盖的步骤; 在所述阻挡金属层上形成金属层以使得所述开口嵌入的步骤; 抛光步骤，通过使用阻挡金属层作为阻挡层进行研磨来去除阻挡金属层上的金属层，使得形成包含金属层的布线层嵌入开口和阻挡金属层中; 以及在所述布线层上制造TMR元件的元件制造步骤。

公开(公告)号：US06638403B1

公开(公告)日：2003-10-28

申请号：US09644072

申请日：2000-08-23

申请人： Hiroshi Inaba ,  Shinji Sasaki ,  Shinya Hirano ,  Kenji Furusawa ,  Minoru Yamasaka ,  Atsushi Amatatsu ,  Shi Xu

发明人： Hiroshi Inaba ,  Shinji Sasaki ,  Shinya Hirano ,  Kenji Furusawa ,  Minoru Yamasaka ,  Atsushi Amatatsu ,  Shi Xu

IPC分类号： C23C1400

CPC分类号： H01J37/32055 ,  C23C14/325 ,  H01J37/3266

摘要： In the plasma processing device which utilizes a low pressure arc discharge, a method for efficiently capturing and removing electrically charged particles and neutral particles having no charge which are at most 5 &mgr;m in particle diameter is demanded. The electrically charged particles can be captured efficiently by installing an electric field filter in a transportation course of plasma. The electric field filter has a cylindrical structure which is uneven in inner wall shape. A voltage in the range of 10 to 90 V is applied to the electric field filter. The neutral filters can be captured efficiently by installing a neutral filter having an opening sectional area which is at most 40% of a sectional area of the transportation course.

摘要翻译： 在使用低压电弧放电的等离子体处理装置中，要求有效地捕获和去除带电粒子的方法和粒径不超过5μm的无电荷的中性粒子。 通过在等离子体的输送过程中安装电场滤波器可以有效地捕获带电粒子。 电场滤波器具有内壁形状不均匀的圆筒状结构。 对电场滤波器施加10〜90V范围的电压。 可以通过安装具有开口截面积至多为运输路线横截面面积的40％的中性过滤器来有效地捕获中性过滤器。

公开(公告)号：US20110049657A1

公开(公告)日：2011-03-03

申请号：US12870486

申请日：2010-08-27

申请人： Keisuke TSUKAMOTO ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

发明人： Keisuke TSUKAMOTO ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

IPC分类号： H01L29/82 ,  H01L21/18

CPC分类号： H01L27/105 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.

摘要翻译： 提供一种半导体器件，其中减小了电阻元件等中的短路故障及其制造方法。 其中形成存储单元的层间绝缘膜形成为使得位于形成有磁阻元件的存储单元区域中的层间绝缘膜的部分的上表面位于比上表面的位置低的位置 层间绝缘膜的位于周边区域的部分。 形成另一层间绝缘膜以覆盖磁阻元件。 在另一个层间绝缘膜中，形成电耦合到磁阻元件的位线。 在磁阻电阻元件的正下方形成数位线。

公开(公告)号：US20230306634A1

公开(公告)日：2023-09-28

申请号：US18124075

申请日：2023-03-21

申请人： SHIROKI CORPORATION ,  TAMADIC Co., Ltd. ,  Shinya Hirano ,  TACT SYSTEM Co., Ltd.

发明人： Yu OKUMURA ,  Naofumi Matsushita ,  Junya Nakamura ,  Tomokazu Uchiyama ,  Shinji Fujino ,  Motohiro Kakureya ,  Kohei Yagi ,  Shinya Hirano ,  Hitoshi Fujiyama

IPC分类号： G06T7/73

CPC分类号： G06T7/74 ,  G06T7/75 ,  G06T2207/30164

摘要： There is provided a target detection method and detection device that can detect a target by a simple method and configuration.
A target detection method includes: a step of, at a first position information generation device, measuring a position and a posture of a first target; a step of, at a second position information generation device, measuring the position and the posture of the first target; a step of calculating a position and a posture of one of the first position information generation device and the second position information generation device with respect to other one of the first position information generation device and the second position information generation device based on a difference between the position and the posture of the first target measured by the first position information generation device, and the position and the posture of the first target measured by the second position information generation device; and a step of, at the second position information generation device, measuring a position and a posture of a second target using the position and the posture of the one of the first position information generation device and the second position information generation device with respect to the other one of the first position information generation device and the second position information generation device.

公开(公告)号：US10906183B2

公开(公告)日：2021-02-02

申请号：US15954092

申请日：2018-04-16

申请人： Toyota Jidosha Kabushiki Kaisha ,  Tamadic Co., Ltd. ,  Shinya Hirano

发明人： Motoyasu Machino ,  Kazuki Yokouchi ,  Masato Inagaki ,  Shinya Hirano

IPC分类号： G06F17/00 ,  B25J9/16 ,  B25J9/00

摘要： A calibration system that calibrates robots installed in a process includes: a reference measuring element; a flange measuring element attached to a flange provided at an arm tip of each robot; a fixed measuring device configured to measure the flange measuring element of each robot and the reference measuring element; and a controller configured to control the robots, calculate a position and attitude relation between the flange measuring element of each robot and the reference measuring element based on a measured result measured by the fixed measuring device, and calculate an error between a design installation position and attitude of each robot and an actual installation position and attitude of the robot by using the measured position and attitude relation and position and attitude data of the flange measuring element in a robot coordinate system at the time when the robot has been measured by the fixed measuring device.

公开(公告)号：US08415756B2

公开(公告)日：2013-04-09

申请号：US12870486

申请日：2010-08-27

申请人： Keisuke Tsukamoto ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

发明人： Keisuke Tsukamoto ,  Shinya Hirano ,  Yuichiro Fujiyama ,  Tatsunori Murata

IPC分类号： H01L29/82

CPC分类号： H01L27/105 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.

摘要翻译： 提供一种半导体器件，其中减小了电阻元件等中的短路故障及其制造方法。 其中形成存储单元的层间绝缘膜形成为使得位于形成有磁阻元件的存储单元区域中的层间绝缘膜的部分的上表面位于比上表面的位置低的位置 层间绝缘膜的位于周边区域的部分。 形成另一层间绝缘膜以覆盖磁阻元件。 在另一个层间绝缘膜中，形成电耦合到磁阻元件的位线。 在磁阻电阻元件的正下方形成数位线。

公开(公告)号：US20070134920A1

公开(公告)日：2007-06-14

申请号：US11556382

申请日：2006-11-03

申请人： Shinya Hirano ,  Yoshimi Sudo ,  Tetsunori Imaizumi ,  Yasuhiro Yoshida

发明人： Shinya Hirano ,  Yoshimi Sudo ,  Tetsunori Imaizumi ,  Yasuhiro Yoshida

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  H01L21/02068 ,  H01L21/321 ,  H01L21/76877 ,  H01L21/76883

摘要： A Cu wiring formation method comprises the steps of: forming a Cu film on a wafer by plating; subjecting the Cu film to anticorrosive treatment on the surface thereof after the plating; and annealing the Cu film after the anticorrosive treatment.

摘要翻译： Cu布线形成方法包括以下步骤：通过电镀在晶片上形成Cu膜; 在镀覆之后对其表面进行Cu膜的耐腐蚀处理; 并在防腐处理后退火Cu膜。