公开(公告)号：US08154909B2

公开(公告)日：2012-04-10

申请号：US13165551

申请日：2011-06-21

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3

摘要翻译： 本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL） 使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

公开(公告)号：US20100172171A1

公开(公告)日：2010-07-08

申请号：US12602414

申请日：2008-05-15

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3

摘要翻译： 本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL） 使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与所选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

公开(公告)号：US07990754B2

公开(公告)日：2011-08-02

申请号：US12602414

申请日：2008-05-15

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2≦V3

摘要翻译： 本发明的电阻可变存储装置（100）具有与各个电阻变化层（114）串联连接且阈值电压为VF的电流抑制元件（116），并且将第一电压V1 与所选择的非易失性存储器元件相关联的第一线（WL）将第二电压V2施加到与所选择的非易失性存储器元件相关联的第二线（BL），将第三电压V3施加到不相关联的第一线（WL） 使用所选择的非易失性存储元件，并且在写入数据或读取数据时将第四电压V4施加到与所选择的存储器元件不相关联的第二电线（BL），其中V2＆nlE; V3

公开(公告)号：US20100046273A1

公开(公告)日：2010-02-25

申请号：US12513914

申请日：2008-06-20

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Yoshihiko Kanazawa

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Yoshihiko Kanazawa

IPC分类号： G11C11/00 ,  G11C11/36 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).

摘要翻译： 存储单元（MC）形成在沿X方向延伸的位线（BL）和在Y方向上延伸的字线（WL）的交点处。 在Y方向并排配置有分别形成为在Z方向排列的一组位线（BL）的字线（WL）的多个基本阵列平面。 在每个基本阵列平面中，偶数层中的位线和奇数层中的位线共同单独连接。 每个选择开关元件（101至104）控制共用连接偶数层位线与全局位线（GBL）之间的电连接/非连接的切换，并且每个选择开关元件（111至114）控制切换 共同连接的奇数位位线和全局位线（GBL）之间的连接/非连接。

公开(公告)号：US07920408B2

公开(公告)日：2011-04-05

申请号：US12513914

申请日：2008-06-20

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Yoshihiko Kanzawa

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Yoshihiko Kanzawa

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).

摘要翻译： 存储单元（MC）形成在沿X方向延伸的位线（BL）和在Y方向上延伸的字线（WL）的交点处。 在Y方向并排配置有分别形成为在Z方向排列的一组位线（BL）的字线（WL）的多个基本阵列平面。 在每个基本阵列平面中，偶数层中的位线和奇数层中的位线共同单独连接。 每个选择开关元件（101至104）控制共用连接偶数层位线与全局位线（GBL）之间的电连接/非连接的切换，并且每个选择开关元件（111至114）控制切换 共同连接的奇数位位线和全局位线（GBL）之间的连接/非连接。

公开(公告)号：US08687409B2

公开(公告)日：2014-04-01

申请号：US13639120

申请日：2012-05-30

申请人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Ryotaro Azuma ,  Ken Kawai

发明人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Ryotaro Azuma ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72

摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.

摘要翻译： 一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器 包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以 最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

公开(公告)号：US20130077384A1

公开(公告)日：2013-03-28

申请号：US13636169

申请日：2012-04-27

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

IPC分类号： G11C11/21

CPC分类号： G11C11/21 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/15 ,  G11C2213/71

摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.

摘要翻译： 一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一 恒定电流被提供给未选择的字线。

公开(公告)号：US08305795B2

公开(公告)日：2012-11-06

申请号：US12999019

申请日：2010-04-27

申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).

摘要翻译： 为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。 在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻 州（401）。

公开(公告)号：US20110122680A1

公开(公告)日：2011-05-26

申请号：US13054312

申请日：2010-04-14

申请人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

发明人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。

公开(公告)号：US20130148406A1

公开(公告)日：2013-06-13

申请号：US13700329

申请日：2012-07-11

申请人： Kazuhiko Shimakawa ,  Kiyotaka Tsuji ,  Ryotaro Azuma

发明人： Kazuhiko Shimakawa ,  Kiyotaka Tsuji ,  Ryotaro Azuma

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/0004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/77

摘要： A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.

摘要翻译： 提供一种能够抑制潜流引起的对存储元件的电阻值的检测灵敏度的降低的交叉点非易失性存储装置。 该设备包括垂直位和字线; 交叉点单元阵列，其包括存储单元，每个存储单元具有电阻值，该电阻值根据电信号在至少两个电阻状态之间可逆地改变;布置在字和位线的交叉点上; 偏移检测单元阵列，包括在高电阻状态下具有高于存储单元的电阻的偏移检测单元，所述字线由偏移检测单元阵列共享; 读取电路（读出放大器），其基于通过所选位线的电流确定所选存储单元的电阻状态; 以及在读取操作时段中向偏移检测单元阵列提供电流的电流源。