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    SEMICONDUCTOR INTEGRATED CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20120286853A1

    公开(公告)日：2012-11-15

    申请号：US13559403

    申请日：2012-07-26

    申请人： Ryouhei SEKI ,  Hideyuki Kabuo

    发明人： Ryouhei SEKI ,  Hideyuki Kabuo

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0016

    摘要： A semiconductor integrated circuit includes a main circuit including a transistor, a pseudo-power supply line connected to a first power supply terminal of the main circuit, a first power supply line connected to the pseudo-power supply line via a first switch, a second power supply line connected to a second power supply terminal of the main circuit, a diode having a first end connected to the pseudo-power supply line and a second end connected to the first power supply line so that a potential difference between the pseudo-power supply line and the second power supply line is reduced in a conductive state, and a second switch having a first end connected to the pseudo-power supply line and a second end connected to the second power supply line.

    摘要翻译： 半导体集成电路包括：主电路，包括晶体管，连接到主电路的第一电源端的伪电源线，经由第一开关连接到伪电源线的第一电源线;第二 电源线连接到主电路的第二电源端子，二极管，其第一端连接到伪电源线，第二端连接到第一电源线，使得伪功率 供电线路和第二电源线路处于导通状态，第二开关具有连接到伪电源线的第一端和连接到第二电源线的第二端。

    Processing unit and processing method
    4.
    发明授权
    Processing unit and processing method 有权
    处理单元及处理方法

    公开(公告)号：US06735714B2

    公开(公告)日：2004-05-11

    申请号：US10252394

    申请日：2002-09-24

    申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

    发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

    IPC分类号： G06F1100

    CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

    摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.

    摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。

    Data processing system and register file
    5.
    发明授权
    Data processing system and register file 有权

    公开(公告)号：US06334135B2

    公开(公告)日：2001-12-25

    申请号：US09811700

    申请日：2001-03-20

    申请人： Hideyuki Kabuo

    发明人： Hideyuki Kabuo

    IPC分类号： G06F1500

    CPC分类号： G06F7/57 ,  G06F7/4991 ,  G06F7/49921 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30105 ,  G06F9/3865

    摘要： A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.

    Substitute register for use in a high speed data processor
    6.
    发明授权
    Substitute register for use in a high speed data processor 有权
    替代寄存器用于高速数据处理器

    公开(公告)号：US06260136B1

    公开(公告)日：2001-07-10

    申请号：US09135487

    申请日：1998-08-18

    申请人： Hideyuki Kabuo

    发明人： Hideyuki Kabuo

    IPC分类号： G06F9302

    CPC分类号： G06F9/3001 ,  G06F9/30101 ,  G06F9/30141

    摘要： In addition to a register file having four general-purpose registers each for storing data, an arithmetic and logic unit for executing an addition instruction, a subtraction instruction, or the like, and a multiplier unit for executing a multiplication instruction, there are provided a controller and a substitute register for storing only data representing the result of operation performed by the multiplier unit in place of any of the four general-purpose registers in the register file. The controller controls the writing and reading of data in and from the register file and the writing and reading of data in and from the substitute register based on a multiplication tag indicative of the one of the four general-purpose registers in place of which the substitute register stores the data representing the result of multiplication and on a multiplication execute flag indicative of whether the data stored in the substitute register is effective or ineffective.

    摘要翻译： 除了具有四个用于存储数据的通用寄存器的寄存器文件之外，还包括用于执行加法指令的算术和逻辑单元，减法指令等，以及用于执行乘法指令的乘法器单元， 控制器和替代寄存器，用于仅存储表示乘法器单元执行的操作结果的数据，代替寄存器文件中的四个通用寄存器中的任一个。 控制器控制在寄存器文件中写入和读取数据，以及根据指示四个通用寄存器之一的乘法标签代替替代寄存器中的数据的写入和读取，代替替换 寄存器存储表示乘法结果的数据，以及表示存储在替代寄存器中的数据是有效还是无效的乘法执行标志。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC INFORMATION DEVICE
    7.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC INFORMATION DEVICE 审中-公开
    半导体集成电路和电子信息设备

    公开(公告)号：US20110210748A1

    公开(公告)日：2011-09-01

    申请号：US13103753

    申请日：2011-05-09

    申请人： Ryota NISHIKAWA ,  Hideyuki Kabuo

    发明人： Ryota NISHIKAWA ,  Hideyuki Kabuo

    IPC分类号： G01R31/02

    CPC分类号： G01R31/31715 ,  H01L27/088

    摘要： A semiconductor integrated circuit and an electronic information device each of which can detect a fault at one of control signals of tristate gates with a smaller area than conventional ones and without reducing the speed of normal operation, by providing a fault detector using tristate gates.

    摘要翻译： 一种半导体集成电路和电子信息装置，通过提供使用三态门的故障检测器，每一个可以以比传统门的区域小的三态门的控制信号中的一个检测故障，并且不降低正常操作的速度。

    Processing unit and processing method
    8.
    发明授权
    Processing unit and processing method 有权
    处理单元及处理方法

    公开(公告)号：US07139968B2

    公开(公告)日：2006-11-21

    申请号：US10748242

    申请日：2003-12-31

    申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

    发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

    IPC分类号： H03M13/03

    CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

    摘要： A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

    摘要翻译： 被配置为执行维特比算法的数字信号处理器包括取指令的指令取出单元和对由指令取出单元取出的指令进行解码的解码单元。 数字信号处理器还包括执行由解码单元解码的指令的执行单元。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较，并且执行单元输出新的路径度量。 第一数据，第二数据，第三数据和第四数据中的每一个是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。

    Data processing system and register file
    9.
    发明授权
    Data processing system and register file 有权
    数据处理系统和注册文件

    公开(公告)号：US06282558B1

    公开(公告)日：2001-08-28

    申请号：US09213369

    申请日：1998-12-17

    申请人： Hideyuki Kabuo

    发明人： Hideyuki Kabuo

    IPC分类号： G06F738

    CPC分类号： G06F7/57 ,  G06F7/4991 ,  G06F7/49921 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30105 ,  G06F9/3865

    摘要： A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.

    摘要翻译： 通过各个地址识别的多个单元被布置在寄存器文件中。 每个单元具有用于存储表示算术运算结果的数据的数据寄存器，用于存储指示在算术运算中是否存在溢出的溢出标志的寄存器，以及用于存储符号标志的寄存器 提供在算术运算中出现溢出的情况下，正和负饱和值中的哪一个应代替算术运算结果的指示。 响应于关于其对应的寄存器的写入信号来更新每个标志。 如果在数据寄存器被馈送读取信号的时刻，则设置相应的溢出标志，则在运算单元的输入侧产生正或负的饱和值，取决于符号标志。

    Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control
    10.
    发明授权
    Method and circuit for delayed branch control and method and circuit for conditional-flag rewriting control 失效

    公开(公告)号：US5996069A

    公开(公告)日：1999-11-30

    申请号：US865160

    申请日：1997-05-29

    申请人： Hiroyuki Yasoshima ,  Hideyuki Kabuo

    发明人： Hiroyuki Yasoshima ,  Hideyuki Kabuo

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/30094 ,  G06F9/30061 ,  G06F9/3842

    摘要： In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability. The branch-information storing circuit can simply be composed of a combination of a shift register, a counter, and a latch.