公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US4939690A

公开(公告)日：1990-07-03

申请号：US290427

申请日：1988-12-27

申请人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其包括NAND单元块，每个NAND单元具有连接到相应位线的选择晶体管和存储单元晶体管的串联阵列。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据擦除模式下，通过向存储单元的控制栅极施加“H”电平电位，并将位线的“L”电平电位同时擦除所有存储单元。 在这种同时擦除之前，从存储器单元的电荷累积层去除电荷，使得存储单元的阈值被初始化。 对NAND单元块中的串联存储单元晶体管依次执行阈值初始化。

公开(公告)号：US5597748A

公开(公告)日：1997-01-28

申请号：US247589

申请日：1994-05-23

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5824583A

公开(公告)日：1998-10-20

申请号：US949819

申请日：1997-10-14

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5323039A

公开(公告)日：1994-06-21

申请号：US499342

申请日：1990-06-21

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。 公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US09580791B2

公开(公告)日：2017-02-28

申请号：US13697164

申请日：2011-04-26

申请人： Satoshi Inoue ,  Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda

发明人： Satoshi Inoue ,  Shinichi Kawato ,  Nobuhiro Hayashi ,  Tohru Sonoda

IPC分类号： C23C16/04 ,  H05B33/10 ,  C23C14/04 ,  B05C21/00 ,  H01L51/00 ,  H01L51/50

CPC分类号： C23C14/042 ,  B05C21/005 ,  H01L51/0011 ,  H01L51/50

摘要： A vapor deposition mask (70) includes a first layer (71), a second layer (72) and a third layer (73) in this order. A plurality of first openings (71h), a plurality of second openings (72h) and a plurality of third openings (73h) are formed respectively in the first layer, the second layer and the third layer. The first openings, the second openings and the third openings communicate with each other, thereby constituting mask openings (75). The opening dimension of the second openings is larger than the opening dimension of the first openings and is larger than the opening dimension of the third openings. With this configuration, it is possible to prevent reduction of the opening dimension of the mask openings or clogging of the mask openings due to the vapor deposition particles adhering to the mask openings.

摘要翻译： 蒸镀掩模（70）依次包括第一层（71），第二层（72）和第三层（73）。 多个第一开口（71h），多个第二开口（72h）和多个第三开口（73h）分别形成在第一层，第二层和第三层中。 第一开口，第二开口和第三开口彼此连通，从而构成掩模开口（75）。 第二开口的开口尺寸大于第一开口的开口尺寸，并且大于第三开口的开口尺寸。 利用这种构造，可以防止由于气相沉积颗粒粘附到掩模开口而导致的掩模开口的开口尺寸的减小或掩模开口的堵塞。

公开(公告)号：US09391275B2

公开(公告)日：2016-07-12

申请号：US13703873

申请日：2011-08-17

申请人： Tohru Sonoda ,  Nobuhiro Hayashi ,  Shinichi Kawato ,  Satoshi Inoue

发明人： Tohru Sonoda ,  Nobuhiro Hayashi ,  Shinichi Kawato ,  Satoshi Inoue

IPC分类号： C23C16/00 ,  H01L51/00 ,  C23C14/04 ,  H01L27/32 ,  H01L51/56

CPC分类号： H01L51/0008 ,  C23C14/042 ,  H01L27/3211 ,  H01L27/3244 ,  H01L51/0011 ,  H01L51/56

摘要： A vapor deposition source (60), a plurality of control plates (80) and a vapor deposition mask (70) are disposed in this order. A substrate (10) is moved relative to the vapor deposition mask in a state in which the substrate and the vapor deposition mask are spaced apart at a fixed interval. Vapor deposition particles (91) discharged from a vapor deposition source opening (61) of the vapor deposition source pass through neighboring inter-control plate spaces (81) and mask openings (71) formed in the vapor deposition mask, and then adhere to the substrate to form a coating film (90). At least a part of the coating film is formed by the vapor deposition particles that have passed through two or more different inter-control plate spaces. It is thereby possible to form a coating film in which edge blur and variations in the thickness are suppressed.

摘要翻译： 蒸镀源（60），多个控制板（80）和蒸镀掩模（70）依次配置。 在基板和气相沉积掩模以固定间隔间隔开的状态下，基板（10）相对于气相沉积掩模移动。 从气相沉积源的气相沉积源开口（61）排出的气相沉积颗粒（91）通过相邻的控制板间隙（81）和形成在气相沉积掩模中的掩模开口（71），然后粘附到 基板以形成涂膜（90）。 涂膜的至少一部分由已经通过两个或更多个不同的控制间隙的气相沉积颗粒形成。 由此，可以形成抑制边缘模糊和厚度变化的涂膜。

公开(公告)号：US08845808B2

公开(公告)日：2014-09-30

申请号：US13997173

申请日：2011-12-19

申请人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

发明人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

IPC分类号： C23C14/26 ,  C23C16/448 ,  H05B33/10 ,  C23C14/24 ,  H01L21/02 ,  H01L51/00 ,  H01L51/56

CPC分类号： C23C16/45578 ,  C23C14/24 ,  C23C14/243 ,  H01L21/02263 ,  H01L51/001 ,  H01L51/56 ,  H05B33/10

摘要： A vapor deposition device (50) in accordance with the present invention is a vapor deposition device for forming a film on a film formation substrate (60), the vapor deposition device including a vapor deposition source (80) that has an injection hole (81) from which vapor deposition particles are injected, a vapor deposition particle crucible (82) for supplying the vapor deposition particles to the vapor deposition source (80), and a rotation motor (86) for changing a distribution of the injection amount of the vapor deposition particles by rotating the vapor deposition source (80).

摘要翻译： 根据本发明的蒸镀装置（50）是在成膜基板（60）上形成膜的蒸镀装置，其特征在于，所述蒸镀装置具有：蒸镀源（80），具有喷射孔 ），用于将气相沉积粒子供给到气相沉积源（80）的气相沉积粒子坩埚（82）和用于改变蒸汽喷射量分布的旋转马达（86） 通过旋转气相沉积源（80）来沉积颗粒。

公开(公告)号：US08673082B2

公开(公告)日：2014-03-18

申请号：US13980875

申请日：2012-01-13

申请人： Satoshi Inoue ,  Shinichi Kawato ,  Tohru Sonoda

发明人： Satoshi Inoue ,  Shinichi Kawato ,  Tohru Sonoda

IPC分类号： C23C16/00

CPC分类号： C23C16/448 ,  C23C14/243 ,  C23C16/042 ,  G03B37/06 ,  H01L51/0008

摘要： A crucible (50) of the present invention includes: an opening (55a) from which vapor deposition particles are injected toward a film formation substrate on which a film is to be formed; a focal point member (54a), provided so as to face the opening (55a), which reflects vapor deposition particles injected from the opening (55a); and a revolution paraboloid (55b) which reflects, toward the film formation substrate, vapor deposition particles which have been reflected by the focal point member (54a).

摘要翻译： 本发明的坩埚（50）包括：朝向要在其上形成膜的成膜基板上注入蒸镀颗粒的开口（55a） 设置成面对开口（55a）的焦点部件（54a），其反射从开口（55a）喷射的气相沉积粒子; 以及向所述成膜基板反射已被所述焦点部件（54a）反射的气相沉积粒子的旋转抛物面（55b）。

公开(公告)号：US20140014036A1

公开(公告)日：2014-01-16

申请号：US14007956

申请日：2012-03-23

申请人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

发明人： Tohru Sonoda ,  Shinichi Kawato ,  Satoshi Inoue ,  Satoshi Hashimoto

IPC分类号： H01L21/02 ,  B65D85/00

摘要： A vapor deposition particle emitting device of the present invention includes: a nozzle section (110) having emission holes (111) from which gaseous vapor deposition particles are emitted out; a heating plate unit (100), provided in the nozzle section (110), which is made up of heating plates (101) each having a surface on which a vapor deposition material remains as a result of adherence of vapor deposition particles to the surface; and a heating device (160) for heating the vapor deposition material, which is thus remaining on the surface of each of the heating plates (101), so that a temperature of the vapor deposition material is not less than a temperature at which to become transformed into gaseous form.

摘要翻译： 本发明的气相沉积粒子发射装置包括：喷嘴部分（110），其具有从其中排出气态气相沉积颗粒的发射孔（111）; 设置在所述喷嘴部分（110）中的加热板单元（100），所述加热板单元由加热板（101）组成，所述加热板具有由于气相沉积颗粒粘附到所述表面而具有气相沉积材料的表面的表面 ; 以及用于加热蒸镀材料的加热装置（160），其被保持在每个加热板（101）的表面上，使得蒸镀材料的温度不低于成为 转化成气态。