公开(公告)号：US5663905A

公开(公告)日：1997-09-02

申请号：US469161

申请日：1995-06-06

申请人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

发明人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/401 ,  H01L27/10 ,  H01L27/105 ,  G11C11/24

CPC分类号： H01L27/105 ,  G11C11/005

摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

摘要翻译： 半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。 动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。 静态存储单元阵列被布置成与动态存储单元阵列相邻。 静态存储单元阵列包括以矩阵形状排列的静态存储单元。 多个字线被布置成多行。 每个字线连接到布置在相应行中的动态和静态存储单元。 多个DRAM位线对排列成多列。 每个DRAM位线对连接到动态存储单元。 在其他多个列中布置有多个SRAM位线对。 每个SRAM位线对连接到布置在相应列中的静态存储单元。

公开(公告)号：US5781468A

公开(公告)日：1998-07-14

申请号：US851757

申请日：1997-05-06

申请人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

发明人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/401 ,  H01L27/10 ,  H01L27/105 ,  G11C11/24

CPC分类号： H01L27/105 ,  G11C11/005

摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

摘要翻译： 半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。 动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。 静态存储单元阵列被布置成与动态存储单元阵列相邻。 静态存储单元阵列包括以矩阵形状排列的静态存储单元。 多个字线被布置成多行。 每个字线连接到布置在相应行中的动态和静态存储单元。 多个DRAM位线对排列成多列。 每个DRAM位线对连接到动态存储单元。 在其他多个列中布置有多个SRAM位线对。 每个SRAM位线对连接到布置在相应列中的静态存储单元。

公开(公告)号：US06301678B1

公开(公告)日：2001-10-09

申请号：US09167713

申请日：1998-10-07

申请人： Hirotoshi Sato ,  Tomohisa Wada ,  Shigeki Ohbayashi

发明人： Hirotoshi Sato ,  Tomohisa Wada ,  Shigeki Ohbayashi

IPC分类号： G11C2900

CPC分类号： G11C29/48

摘要： In a semiconductor memory device having a plurality of data input/output pins, control pins (e.g. address pins and external control signal pins) are arranged parallel to each other on a chip. The plurality of data input/output pins are divided into a plurality of groups. Each group has a specific data input/output pin. The specific data input/output pin is lined up with the control pins. In a test mode, a signal is written into all memory cells by applying the signal to the specific data input/output pin. In addition, whether the signals read from all memory cells are correct or not is determined using the specific data input/output pin.

摘要翻译： 在具有多个数据输入/输出引脚的半导体存储器件中，控制引脚（例如地址引脚和外部控制信号引脚）在芯片上彼此平行布置。 多个数据输入/输出引脚被分成多个组。 每组有一个特定的数据输入/输出引脚。 具体的数据输入/输出引脚与控制引脚对齐。 在测试模式下，通过将信号施加到特定数据输入/输出引脚，将信号写入所有存储单元。 此外，使用特定数据输入/输出引脚确定从所有存储单元读取的信号是否正确。

公开(公告)号：US5659515A

公开(公告)日：1997-08-19

申请号：US520190

申请日：1995-08-28

申请人： Ryuichi Matsuo ,  Tomohisa Wada

发明人： Ryuichi Matsuo ,  Tomohisa Wada

IPC分类号： G11C7/10 ,  G11C11/401 ,  G11C11/405 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C7/103 ,  G11C11/406

摘要： A semiconductor memory device comprising a memory cell array, a row decoder, an input/output register train, a burst counter, an input/output bus, a refresh counter and a multiplexer. The memory cell array includes a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells. The input/output register train has a plurality of registers corresponding to the bit line pairs. Each of the registers is connected to the corresponding bit line pair. The input/output bus inputs and outputs data to and from the register train in response to a signal from the burst counter. The multiplexer supplies the row decoder with an external address signal as an internal address signal. After data is transferred from any bit line pair to the register or before data is transferred from any register to the bit line pair, the multiplexer supplies the row decoder with a refresh address signal from the refresh counter in place of the external address signal. This allows a refresh operation to take place during a burst read/write operation of data.

摘要翻译： 包括存储单元阵列，行解码器，输入/输出寄存器列，突发计数器，输入/输出总线，刷新计数器和多路复用器的半导体存储器件。 存储单元阵列包括多个字线，多个位线对和多个存储单元。 输入/输出寄存器列具有对应于位线对的多个寄存器。 每个寄存器都连接到相应的位线对。 输入/输出总线响应于来自脉冲串计数器的信号，输入和输出数据到和从寄存器串中输出数据。 多路复用器为行解码器提供外部地址信号作为内部地址信号。 在数据从任何位线对传输到寄存器之后，或者在数据从任何寄存器传送到位线对之前，多路复用器为行解码器提供来自刷新计数器的刷新地址信号来代替外部地址信号。 这允许在数据的突发读/写操作期间进行刷新操作。

公开(公告)号：US07902481B2

公开(公告)日：2011-03-08

申请号：US11547323

申请日：2005-03-30

申请人： Keisuke Kigawa ,  Haruyuki Hiratsuka ,  Tomohisa Wada

发明人： Keisuke Kigawa ,  Haruyuki Hiratsuka ,  Tomohisa Wada

IPC分类号： H01L21/50 ,  B23K26/20

CPC分类号： H03H9/1021 ,  H01L21/50 ,  H03H3/02

摘要： A method of manufacturing a sealed electronic component, which can seal a housing in a high-vacuum state while preventing enclosure of a gas within the housing, as well as achieving the improvement in manufacturing efficiency. According to the method, after forming an unwelded section by a primary welding process step, including a first beam irradiation process step and a second beam irradiation process step, annealing treatment is performed in an annealing process step by irradiating an electron beam to a predetermined portion on a locus of the electron beam formed in the first beam irradiation process step. The locus may be on a housing or a lid.

摘要翻译： 一种制造密封电子部件的方法，其可以在高真空状态下密封壳体，同时防止气体在壳体内的封闭，以及实现制造效率的提高。 根据该方法，在通过一次焊接工艺步骤形成未焊接部分之后，包括第一光束照射处理步骤和第二光束照射处理步骤，在退火处理步骤中通过将电子束照射到预定部分 在第一光束照射处理步骤中形成的电子束的轨迹上。 轨迹可以在壳体或盖子上。

公开(公告)号：US06327188B1

公开(公告)日：2001-12-04

申请号：US09477560

申请日：2000-01-04

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C1300

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for external output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果它们之间发现匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓存存储器的高速操作，并且实现诸如超级计算机， 大型计算器，工作站和个人计算机可以改进。

公开(公告)号：US5724292A

公开(公告)日：1998-03-03

申请号：US781386

申请日：1997-01-13

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C11/419 ,  G11C7/02

CPC分类号： G11C11/419

摘要： Sense circuits are provided correspondingly to bit line pairs provided corresponding to memory cell columns, respectively. The sense circuit senses, amplifies and latches storage data of the selected memory cell, and information latched by the sense amplifier is rewritten into the selected memory cell after selection of the memory cell. Thereby, destruction of storage information of the memory cell is prevented.

摘要翻译： 对应于分别对应于存储单元列提供的位线对提供感测电路。 感测电路感测，放大和锁存所选择的存储单元的存储数据，并且在选择存储单元之后，读出放大器锁存的信息被重写到所选存储单元中。 从而防止了存储单元的存储信息的破坏。

公开(公告)号：US5687111A

公开(公告)日：1997-11-11

申请号：US609313

申请日：1996-03-01

申请人： Tomohisa Wada ,  Kunihiko Kozaru ,  Toru Shiomi

发明人： Tomohisa Wada ,  Kunihiko Kozaru ,  Toru Shiomi

IPC分类号： G11C11/411 ,  G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00 ,  H01L27/02

CPC分类号： H01L27/1112 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  Y10S257/903

摘要： A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.

摘要翻译： 横向型T1和T2的一对驱动双极晶体管具有耦合到接地电位的发射极，与一对高电阻元件R1和R2连接的集电极。 高电阻元件R1和R2具有耦合到电源电位VCC的相应的另一端，并且晶体管T1和T2的基极和集电极彼此交叉连接，从而形成触发电路。 具有由字线WL控制的栅极电位的接入MOS晶体管Q3和Q4分别被连接以形成存储节点A和B之一与一对位线BL和/ BL中的一个之间的导通路径。

公开(公告)号：US5546352A

公开(公告)日：1996-08-13

申请号：US354760

申请日：1994-12-12

申请人： Hirotoshi Sato ,  Tomohisa Wada

发明人： Hirotoshi Sato ,  Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/06 ,  G11C11/407 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C8/06

摘要： In the present invention, a row address processing circuit and a column address processing circuit operate in synchronism with an externally applied synchronous signal in a semiconductor memory device. The row address processing circuit and the column address processing circuit each include an address buffer and a decoder. The address buffer or decoder operates in synchronism with the synchronous signal.

摘要翻译： 在本发明中，行地址处理电路和列地址处理电路与半导体存储器件中外部施加的同步信号同步工作。 行地址处理电路和列地址处理电路各自包括地址缓冲器和解码器。 地址缓冲器或解码器与同步信号同步工作。

公开(公告)号：US5515325A

公开(公告)日：1996-05-07

申请号：US354767

申请日：1994-12-12

申请人： Tomohisa Wada

发明人： Tomohisa Wada

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C13/00

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/00 ,  G11C2207/2218 ,  G11C2207/2245

摘要： An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in which data is not being read out from the memory cell array. A comparator compares the held internal address signal and an internal address signal for reading data. If a matching is found between them, the multiplexer outputs data from the latch circuit for externally output. Accordingly, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost, as a result high speed operation of cache memories is achieved and the speed performance of computers of various levels such as supercomputer, large size calculator, work station and personal computer can be improved.

摘要翻译： 与要写入存储单元的数据对应的内部地址信号保持在锁存电路中。 保持的内部地址信号由下一个写入操作中的多路复用器选择并应用于解码器。 在从存储单元阵列未读出数据的期间，写入数据被锁存电路取入并保持。 比较器比较保持的内部地址信号和用于读取数据的内部地址信号。 如果在它们之间找到匹配，则多路复用器从锁存电路输出数据以进行外部输出。 因此，可以在不增加芯片成本，封装成本和系统成本的情况下消除读取操作之后的写入操作的延迟，从而实现高速缓冲存储器的高速操作以及诸如超级计算机等各种级别的计算机的速度性能， 大型计算器，工作台和个人电脑可以改进。