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公开(公告)号：US20220216233A1
公开(公告)日：2022-07-07
申请号：US17702967
申请日：2022-03-24
发明人： Bongyong LEE , Taehun KIM , Minkyung BAE , Myunghun WOO , Doohee HWANG
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11529 , H01L27/1157 , H01L27/11524
摘要： A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.
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公开(公告)号：US20240065001A1
公开(公告)日：2024-02-22
申请号：US18299403
申请日：2023-04-12
发明人： Seyun KIM , Jooheon KANG , Sunho KIM , Yumin KIM , Garam PARK , Hyunjae SONG , Dongho AHN , Seungyeul YANG , Myunghun WOO , Jinwoo LEE
IPC分类号： H10B63/00
CPC分类号： H10B63/845 , H10B63/34
摘要： Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
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公开(公告)号：US20240164116A1
公开(公告)日：2024-05-16
申请号：US18215280
申请日：2023-06-28
发明人： Youngji NOH , Jongho WOO , Joo-Heon KANG , Kyunghoon KIM , Myunghun WOO
IPC分类号： H10B63/00
CPC分类号： H10B63/845 , H10B63/34
摘要： A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.
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公开(公告)号：US20230165001A1
公开(公告)日：2023-05-25
申请号：US17989061
申请日：2022-11-17
发明人： Jinwoo LEE , Jooheon KANG , Donggeon GU , Doyoon KIM , Yumin KIM , Suseong NOH , Changyup PARK , Hyunjae SONG , Dongho AHN , Myunghun WOO
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.
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公开(公告)号：US20240260280A1
公开(公告)日：2024-08-01
申请号：US18457799
申请日：2023-08-29
发明人： Youngji NOH , Jongho WOO , Joo-Heon KANG , Myunghun WOO
IPC分类号： H10B63/00
CPC分类号： H10B63/845 , H10B63/34
摘要： A semiconductor device including a cell array structure on a semiconductor substrate, the cell array structure including an electrode structure including electrodes and insulating layers vertically and alternately stacked on the semiconductor substrate, and a vertical structure and a penetration contact plug penetrating the electrode structure may be provided. The vertical structure may include a first inner layer, a first outer layer, and a first intermediate layer, and the penetration contact plug may include a second inner layer, a second outer layer, and a second intermediate layer. The electrodes may include a doped semiconductor material, and the first and second outer layers may include the same material. The first and second intermediate layers may include the same material, and the first and second inner layers may include materials different from each other.
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6.发明公开公开(公告)号：US20230269942A1
公开(公告)日：2023-08-24
申请号：US18096257
申请日：2023-01-12
发明人： Myunghun WOO , Jooheon KANG , Hyunmog PARK , Jongho WOO , Suseong NOH , Youngji NOH
摘要： A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.
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公开(公告)号：US20210065809A1
公开(公告)日：2021-03-04
申请号：US16821225
申请日：2020-03-17
发明人： Doohee HWANG , Taehun KIM , Minkyung BAE , Myunghun WOO , Bongyong LEE
摘要： A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.
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