公开(公告)号：US12094941B2

公开(公告)日：2024-09-17

申请号：US17712726

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggwang Kim ,  Sangkoo Kang ,  Donghyun Roh ,  Koungmin Ryu

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/7851

Abstract: A semiconductor device includes a gate structure including a gate electrode, a gate spacer layer on a side surface of the gate electrode, and a gate capping layer on the gate electrode. Moreover, the semiconductor device includes a source/drain region on at least one side of the gate structure, a contact plug on the source/drain region, and first and second insulating films between the contact plug and the gate structure and defining an air gap. The first insulating film includes a first surface, and a second surface extending from the first surface while forming a first angle. The second insulating film includes a third surface forming a second angle with the first surface of the first insulating film. The second angle is an acute angle narrower than the first angle. The air gap is defined by the first surface, the second surface, and the third surface.

公开(公告)号：US11342328B2

公开(公告)日：2022-05-24

申请号：US16943208

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Subin Shin ,  Donghyun Roh ,  Byung-Suk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US11282921B2

公开(公告)日：2022-03-22

申请号：US16903015

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuhwan Ahn ,  Sung Soo Kim ,  Chaeho Na ,  Woongsik Nam ,  Donghyun Roh

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes first and second active patterns on a substrate, the first and second active patterns adjacent to each other in a first direction with a first trench between the first and second active patterns, third and fourth active patterns on the substrate, the third and fourth active patterns adjacent to each other in the first direction with a second trench between the third and fourth active patterns. The semiconductor device includes a first device isolation layer in the first trench, and a second device isolation layer in the second trench. A width of the second trench in the first direction is greater than a width of the first trench in the first direction. The second device isolation layer includes a first protrusion and a second protrusion which protrude from a top surface of the second device isolation layer.

公开(公告)号：US20220077301A1

公开(公告)日：2022-03-10

申请号：US17526634

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkoo Kang ,  Sungsoo Kim ,  Sunki Min ,  Iksoo Kim ,  Donghyun Roh

IPC: H01L29/49 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction on the substrate, the gate structure including a gate electrode, a gate capping layer on the gate electrode, and a plurality of spacers on side surfaces of the gate electrode; source/drain regions on the active region on at least one side of the gate structure; a first insulating layer and a second insulating layer on the source/drain regions on at least one side of the gate structure; and contact plugs on the source/drain regions and penetrating the first and second insulating layers. The plurality of spacers include a first spacer on the side surfaces of the gate electrode, an air-gap spacer on an external side surface of the first spacer, and a second spacer on an external side surface of the air-gap spacer. An upper portion of the second spacer is bent towards an upper portion of the first spacer and is configured to cap the air-gap spacer.

公开(公告)号：US12107122B2

公开(公告)日：2024-10-01

申请号：US18307074

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

公开(公告)号：US20240234542A9

公开(公告)日：2024-07-11

申请号：US18481433

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US12027524B2

公开(公告)日：2024-07-02

申请号：US18200986

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Subin Shin ,  Donghyun Roh ,  Byung-Suk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：US20220367453A1

公开(公告)日：2022-11-17

申请号：US17589178

申请日：2022-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsoo Kim ,  Sunhye Lee ,  Donghyun Roh ,  Koungmin Ryu ,  Jongmin Baek

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/10

Abstract: A semiconductor device includes active fins extending in a first direction on a substrate; an isolation insulating layer covering a portion of side surfaces of the active fins; channel layers stacked vertically and spaced apart on the active fins; a gate pattern in a second direction across the active fins and the channel layers; and spacer layers across the active fins in the second direction on both sides of the gate pattern. At least one spacer layer extends downwardly along a side surface of the gate pattern such that a lower surface thereof contacts the isolation insulating layer. The lower surface of the spacer layer is higher than a level of upper surfaces of the active fins. The gate pattern has a lower surface contacting the isolation insulating layer. The lower surface of the gate pattern is lower than a level of the upper surfaces of the active fins.

公开(公告)号：US20240136426A1

公开(公告)日：2024-04-25

申请号：US18481433

申请日：2023-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungheon Lee ,  Donghyun Roh ,  Jangho Lee

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device, includes forming a mask layer on a semiconductor structure having a plurality of gate lines and a plurality of intergate insulating portions, forming an opening that exposes a cut region of the plurality of gate lines in the mask layer, forming a separation hole by removing a portion of a gate capping layer exposed by the opening, forming a pyrolysis material pattern in the separation hole, forming an etch stop layer on an upper surface of the mask layer and on a side wall portion of the separation hole from which the pyrolysis material pattern is removed, while the pyrolysis material pattern is decomposed and removed, and removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.

公开(公告)号：US11670676B2

公开(公告)日：2023-06-06

申请号：US17379051

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunki Min ,  Donghyun Roh ,  Chaeho Na

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092

Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.