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    METHOD OF ESTIMATING DETERIORATION STATE OF MEMORY DEVICE AND RELATED METHOD OF WEAR LEVELING
    2.
    发明申请
    METHOD OF ESTIMATING DETERIORATION STATE OF MEMORY DEVICE AND RELATED METHOD OF WEAR LEVELING 有权
    估计存储器件的检测状态的方法和相关的磨损等级方法

    公开(公告)号：US20150043282A1

    公开(公告)日：2015-02-12

    申请号：US14446347

    申请日：2014-07-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： BEOM-KYU SHIN ,  UNG-HWAN KIM ,  JUN-JIN KONG ,  EUN-CHEOL KIM ,  DONG-MIN SHIN ,  MYUNG-KYU LEE

    IPC分类号： G11C16/34 ,  G11C16/26

    CPC分类号： G11C11/5642 ,  G06F12/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3495

    摘要： A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.

    摘要翻译： 一种估计存储器件劣化状态的方法包括通过向所选择的字线应用具有对应于至少一个阈值谷值的多个不同读取电压来从连接到存储器单元阵列的选定字线的选定存储单元读取数据 选择的存储单元的电压分布，使用从选择的存储单元读取的数据生成指示阈值电压分布的状态的质量估计信息，并且基于生成的质量估计信息来确定包括所选存储单元的存储区域的劣化状态 。

    STORAGE DEVICE THAT PERFORMS STATE SHAPING OF DATA
    4.
    发明申请
    STORAGE DEVICE THAT PERFORMS STATE SHAPING OF DATA 有权

    公开(公告)号：US20210026734A1

    公开(公告)日：2021-01-28

    申请号：US16835721

    申请日：2020-03-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： YOUNGJUN HWANG ,  DONG-MIN SHIN ,  CHANGKYU SEOL ,  JAEYONG SON ,  HONG RAK SON

    IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/26

    摘要： A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

    MEMORY CONTROLLER, OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM
    5.
    发明申请
    MEMORY CONTROLLER, OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200050513A1

    公开(公告)日：2020-02-13

    申请号：US16357431

    申请日：2019-03-19

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

    IPC分类号： G06F11/10 ,  G06F3/06

    摘要： An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

    MEMORY SYSTEM INCLUDING FIELD PROGRAMMABLE GATE ARRAY (FPGA) AND METHOD OF OPERATING SAME
    8.
    发明申请
    MEMORY SYSTEM INCLUDING FIELD PROGRAMMABLE GATE ARRAY (FPGA) AND METHOD OF OPERATING SAME 有权

    公开(公告)号：US20220035703A1

    公开(公告)日：2022-02-03

    申请号：US17499499

    申请日：2021-10-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： DONG-MIN SHIN ,  HONG-RAK SON

    IPC分类号： G06F11/10 ,  H03M13/29

    摘要： A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM
    9.
    发明申请
    MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM 有权

    公开(公告)号：US20210265005A1

    公开(公告)日：2021-08-26

    申请号：US17317506

    申请日：2021-05-11

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

    IPC分类号： G11C29/42 ,  G06F11/10 ,  G06F3/06

    摘要： An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.