中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.016 seconds)

    APPARATUS THAT RECEIVES NON-BINARY POLAR CODE AND DECODING METHOD THEREOF
    2.
    发明申请
    APPARATUS THAT RECEIVES NON-BINARY POLAR CODE AND DECODING METHOD THEREOF 审中-公开

    公开(公告)号：US20200220652A1

    公开(公告)日：2020-07-09

    申请号：US16566246

    申请日：2019-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JAE-YONG SON ,  CHANG-KYU SEOL ,  HONG-RAK SON ,  PIL-SANG YOON

    IPC: H04L1/00

    Abstract: An apparatus that receives a non-binary polar code through a channel includes a low-complexity decoder and a memory. The low-complexity decoder is configured to selectively calculate first common terms for input symbols in the non-binary polar code other than a first input symbol corresponding to a first target output symbol. The selective calculation uses a lower triangular kernel and log likelihood ratios of the input symbols generated based on a channel characteristic of the channel. The low-complexity decoder is also configured to calculate log likelihood ratios of the first target output symbol using the first common terms and to determine a value of the first target output symbol based on the log likelihood ratios of the first target output symbol. The memory is accessible by the low-complexity decoder and is configured to store the first common terms

    FLASH MEMORY DEVICE, FLASH MEMORY SYSTEM, AND METHODS OF OPERATING THE SAME
    5.
    发明申请
    FLASH MEMORY DEVICE, FLASH MEMORY SYSTEM, AND METHODS OF OPERATING THE SAME 有权
    闪存存储器件，闪存存储器系统及其操作方法

    公开(公告)号：US20150317257A1

    公开(公告)日：2015-11-05

    申请号：US14693300

    申请日：2015-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANG-KYU SEOL ,  SEONG-HYEOG CHOI ,  JUN-JIN KONG ,  HONG-RAK SON

    IPC: G06F12/14 ,  H04L9/32 ,  G06F11/10 ,  G11C29/50 ,  G06F21/31 ,  G06F12/02

    CPC classification number: G11C7/24 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/1425 ,  G06F21/31 ,  G06F2212/1052 ,  G06F2212/7201 ,  G09C1/00 ,  G11C29/50004 ,  G11C2029/0411 ,  G11C2029/5004 ,  H04L9/32 ,  H04L9/3278

    Abstract: Provided are a flash memory device, a flash memory system, and methods of operating the same. A method of operating a flash memory system includes selecting memory cells of a flash memory in response to an authentication challenge, programming pieces of input data into the selected memory cells, respectively, reading the selected memory cells and generating and storing control information, dividing the selected memory cells into at least one first region memory cell and at least one second region memory cell based on the control information, and setting read values of the at least one first region memory cell and the at least one second region memory cell as a first value and a second value, respectively, and generating an authentication response in the response to the authentication challenge.

    Abstract translation: 提供了一种闪存设备，闪存系统及其操作方法。 一种操作闪速存储器系统的方法包括响应于认证挑战选择闪存的存储单元，将输入数据分别编入所选择的存储器单元中，读取所选择的存储器单元并产生和存储控制信息， 将所选择的存储器单元基于所述控制信息输入到至少一个第一区域存储器单元和至少一个第二区域存储器单元中，并且将所述至少一个第一区域存储器单元和所述至少一个第二区域存储器单元的读取值设置为第一 值和第二值，并且在对认证挑战的响应中生成认证响应。

    ERROR CORRECTING CIRCUIT PERFORMING ERROR CORRECTION ON USER DATA AND ERROR CORRECTING METHOD USING THE ERROR CORRECTING CIRCUIT
    6.
    发明申请
    ERROR CORRECTING CIRCUIT PERFORMING ERROR CORRECTION ON USER DATA AND ERROR CORRECTING METHOD USING THE ERROR CORRECTING CIRCUIT 审中-公开

    公开(公告)号：US20200042385A1

    公开(公告)日：2020-02-06

    申请号：US16444056

    申请日：2019-06-18

    Applicant: SAMSUNG ELECTRONICS CO,, LTD.,

    Inventor： YOUNG-JUN HWANG ,  MYUNG-KYU LEE ,  HONG-RAK SON ,  GEUN-YEONG YU ,  Ki-JUN LEE

    IPC: G06F11/10 ,  G11C29/52

    Abstract: An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

    METHOD OF DETERMINING DETERIORATION STATE OF MEMORY DEVICE AND MEMORY SYSTEM USING THE SAME
    7.
    发明申请
    METHOD OF DETERMINING DETERIORATION STATE OF MEMORY DEVICE AND MEMORY SYSTEM USING THE SAME 有权
    用于确定存储器件的检测状态的方法和使用该存储器件的存储器系统

    公开(公告)号：US20140108747A1

    公开(公告)日：2014-04-17

    申请号：US14052801

    申请日：2013-10-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： CHANG-KYU SEOL ,  JUN-JIN KONG ,  HONG-RAK SON

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  G06F11/00 ,  G06F11/1048 ,  G06F11/3466 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3427 ,  G11C16/349 ,  G11C29/00 ,  G11C29/50004 ,  G11C2029/0409

    Abstract: A method is provided for determining a deterioration condition of a memory device. The method includes calculating first information corresponding to a number of bits having a first logic value from data obtained by performing a first read operation on target storage region of the memory device using a first reference voltage as a read voltage, and calculating second information corresponding to a number of bits having a second logic value from data obtained by performing a second read operation on the target storage region using a second reference voltage as the read voltage. A deterioration condition of the target storage region is determined based on the first and second information. The first reference voltage is less than a first read voltage by which an erase state of the memory device is distinguished from an adjacent program state, and the second reference voltage is higher than the first read voltage.

    Abstract translation: 提供了一种用于确定存储器件的劣化状况的方法。 该方法包括：使用第一参考电压作为读取电压，通过对存储器件的目标存储区域执行第一读取操作获得的数据，计算与具有第一逻辑值的位数相对应的第一信息，并且计算对应于 具有来自通过使用第二参考电压作为读取电压对目标存储区域执行第二读取操作获得的数据的第二逻辑值的位数。 基于第一信息和第二信息确定目标存储区域的劣化条件。 第一参考电压小于第一读取电压，通过该第一读取电压将存储器件的擦除状态与相邻的程序状态区分开，并且第二参考电压高于第一读取电压。

    MEMORY SYSTEM INCLUDING FIELD PROGRAMMABLE GATE ARRAY (FPGA) AND METHOD OF OPERATING SAME
    8.
    发明申请
    MEMORY SYSTEM INCLUDING FIELD PROGRAMMABLE GATE ARRAY (FPGA) AND METHOD OF OPERATING SAME 有权

    公开(公告)号：US20220035703A1

    公开(公告)日：2022-02-03

    申请号：US17499499

    申请日：2021-10-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： DONG-MIN SHIN ,  HONG-RAK SON

    IPC: G06F11/10 ,  H03M13/29

    Abstract: A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

Patent Agency Ranking