公开(公告)号：US20180226303A1

公开(公告)日：2018-08-09

申请号：US15856444

申请日：2017-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOSIG WON ,  Sang-Kyu Oh ,  Sungmin Oh ,  Kwangok Jeong

IPC: H01L21/66 ,  H01L21/8238 ,  G01N23/2251 ,  G01R31/26

CPC classification number: H01L22/10 ,  G01N23/2251 ,  G01R31/2644 ,  G01R31/2856 ,  G01R31/307 ,  H01L21/8238 ,  H01L22/12 ,  H01L22/30 ,  H01L27/1104

Abstract: A method of manufacturing a semiconductor device includes forming transistors in a cell region of a test wafer, forming a first test pattern on a first test cell in the cell region, the first test pattern being electrically connected to the transistors, and scanning the first test pattern using an electron beam. Forming the transistors in the cell region includes patterning an upper portion of the test wafer to form active patterns, forming source/drain regions on the active patterns, forming gate electrodes extending across the active patterns, forming active contacts coupled to the source/drain regions, and forming gate contacts coupled to the gate electrodes.

公开(公告)号：US20160056155A1

公开(公告)日：2016-02-25

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-HO PARK ,  TAEJOONG SON ,  SANGHOON BAEK ,  JINTAE KIM ,  GIYOUNG YANG ,  HYOSIG WON

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。

公开(公告)号：US20160056083A1

公开(公告)日：2016-02-25

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  SANGHOON BAEK ,  SUNYOUNG PARK ,  SANG-KYU OH ,  JINTAE KIM ,  HYOSIG WON

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L29/417 ,  H01L21/321 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在器件中比第一触点的顶表面的水平低的水平面上。