公开(公告)号：US20170236921A1

公开(公告)日：2017-08-17

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok MIN ,  Seongjin NAM ,  Sughyun SUNG ,  Youngmook OH ,  Migyeong GWON ,  Hyungdong KIM ,  InWon PARK ,  Hyunggoo LEE

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/683 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/6833 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US20160357630A1

公开(公告)日：2016-12-08

申请号：US15143865

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun KANG ,  Kyoung-nam HA ,  Hyungdong KIM ,  Jun-Phil JUNG

IPC: G06F11/10 ,  G11C29/02 ,  G11C29/52 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H01L25/065 ,  G11C11/4093 ,  G11C29/44

Abstract: The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.

Abstract translation: 半导体存储器件包括包括至少一个缓冲管芯的第一组裸片，并且包括堆叠在第一组上的多个存储器管芯的第二组裸片通过多个TSV线传送数据。 这里，多个存储管芯中的至少一个存储器管芯包括第一型ECC电路，其使用要发送到第一组管芯的发送数据生成传输奇偶校验位，并且缓冲器管芯包括第二类型ECC电路，其在传输时校正 通过多个TSV线接收的发送数据发生误差，使用发送奇偶校验位的发送错误，并生成纠错数据。