公开(公告)号：US20200027855A1

公开(公告)日：2020-01-23

申请号：US16281496

申请日：2019-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon LEE ,  Jiwon SHIN ,  Hyunggil BAEK ,  Minkeun KWAK ,  Jongho LEE

IPC: H01L23/00

Abstract: A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.

公开(公告)号：US20240321775A1

公开(公告)日：2024-09-26

申请号：US18614285

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shlege LEE ,  Hyunggil BAEK ,  Minwoo CHO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/642 ,  H01L25/105 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package comprises: a first package substrate; a semiconductor device mounted on a first surface of the first package substrate and connected to the first package substrate; a plurality of connection pads on a second surface of the first package substrate; a plurality of external connection terminals respectively disposed on one or more connection pads of the plurality of connection pads; a plurality of passive elements mounted on one or more connection pads of the plurality of connection pads in which the plurality of external connection terminals are not disposed; and a floating structure disposed between at least one passive element from the plurality of passive elements and at least one external connection terminal from the plurality of external connection terminals, spaced apart from the at least one passive element and the at least one external connection terminal, and disposed on the second surface of the first package substrate.

公开(公告)号：US20240290750A1

公开(公告)日：2024-08-29

申请号：US18367506

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun LEE ,  Hyunggil BAEK ,  Su-Chang LEE ,  Gyunghwan OH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19041

Abstract: A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.

公开(公告)号：US20230282533A1

公开(公告)日：2023-09-07

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung OH ,  Hyunggil BAEK ,  Seunghwan KIM ,  Jungjoo KIM ,  Jongho PARK ,  Yongkwan LEE

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/5389

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20250166407A1

公开(公告)日：2025-05-22

申请号：US18771182

申请日：2024-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojin SEO ,  Hyunggil BAEK

IPC: G06V40/13

Abstract: A fingerprint sensor package includes a substrate including a plurality of first sensing patterns spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, and a plurality of second sensing patterns spaced apart from each other in the second direction and extending in the first direction; a film substrate defining a through-hole region penetrating the film substrate, the through-hole region overlapping a portion of the substrate in a vertical direction; a controller chip in the through-hole region, the controller chip being electrically connected to the substrate; a plurality of first bonding pads on an upper surface of the film substrate; a plurality of second bonding pads on a lower surface of the substrate; and a plurality of bumps electrically connected between the plurality of first bonding pads and the plurality of second bonding pads.

公开(公告)号：US20230127641A1

公开(公告)日：2023-04-27

申请号：US17862662

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghwan KIM ,  Kyonghwan KOH ,  Jungjoo KIM ,  Jongwan KIM ,  Junwoo PARK ,  Hyunggil BAEK ,  Yongkwan LEE ,  Dongju JANG ,  Taejun JEON

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.

公开(公告)号：US20230039736A1

公开(公告)日：2023-02-09

申请号：US17746454

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngja KIM ,  Hyunggil BAEK ,  Younhwan SHIN

IPC: B28D5/02 ,  C01B32/25

Abstract: A dicing blade includes: a first blade portion and a second blade portion at least partially surrounding the first blade portion, wherein the first blade portion includes: a first bonding layer; first diamond particles disposed in the first bonding layer and having a first density in the first bonding layer; and first metal particles disposed in the first bonding layer, and wherein the second blade portion includes: a second bonding layer at least partially surrounding the first bonding layer; and second diamond particles disposed in the second bonding layer and having a second density in the second bonding layer, wherein the second density is higher than the first density.