公开(公告)号：US08884446B2

公开(公告)日：2014-11-11

申请号：US13792942

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Young-lyong Kim ,  Seong-ho Shin ,  Jae-gwon Jang ,  Jong-ho Lee

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/46 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45664 ,  H01L2924/00012

Abstract: A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Abstract translation: 半导体封装包括堆叠在基板上的主芯片和从芯片。 主芯片和从芯片通过接合线彼此连接。 主芯片和从芯片与外部电路串联连接。 半导体封装可以具有低负载率和优异的性能，并且可以以低成本批量生产。

公开(公告)号：US10923650B2

公开(公告)日：2021-02-16

申请号：US16121266

申请日：2018-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-gwon Jang ,  Baik-woo Lee ,  Young-jae Kim

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/10 ,  H01L23/14 ,  H01L23/049 ,  H01L23/051 ,  H01L43/08 ,  H01L23/00 ,  H01L23/29 ,  H01L23/055 ,  H01L23/06 ,  H01L43/12

Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

公开(公告)号：US09627327B2

公开(公告)日：2017-04-18

申请号：US14815937

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo Lee ,  Dong-hun Lee ,  Jae-gwon Jang ,  Chul-yong Jang

IPC: H01L21/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  B29C70/78 ,  B29K63/00 ,  B29L9/00 ,  B29L31/34 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/552 ,  B29C70/78 ,  B29K2063/00 ,  B29L2009/005 ,  B29L2031/3481 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/85

Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.