公开(公告)号：US20130130472A1

公开(公告)日：2013-05-23

申请号：US13741466

申请日：2013-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Do LEE ,  Jongkook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。

公开(公告)号：US20130241044A1

公开(公告)日：2013-09-19

申请号：US13668852

申请日：2012-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Ki KIM ,  Jung-Do LEE ,  Yang-Hoon AHN ,  Sun-Hye LEE ,  Dae-Young CHOI

IPC: H01L23/48 ,  H01L23/02

CPC classification number: H01L23/36 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to example embodiments, a semiconductor package includes a first semiconductor chip is on a first substrate, a protective layer directly on the first semiconductor chip, and an encapsulant covering an upper surface of the first substrate. The encapsulant may contact side surfaces of the first semiconductor chip and the protective layer.

Abstract translation: 根据示例性实施例，半导体封装包括在第一衬底上的第一半导体芯片，直接在第一半导体芯片上的保护层，以及覆盖第一衬底的上表面的密封剂。 密封剂可以接触第一半导体芯片和保护层的侧表面。