Abstract:
According to example embodiments, a semiconductor package includes a first semiconductor chip is on a first substrate, a protective layer directly on the first semiconductor chip, and an encapsulant covering an upper surface of the first substrate. The encapsulant may contact side surfaces of the first semiconductor chip and the protective layer.
Abstract:
Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.