公开(公告)号：US20170148514A1

公开(公告)日：2017-05-25

申请号：US15298765

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Jin LEE

IPC: G11C13/00 ,  G06F3/06 ,  G11C5/04

CPC classification number: G11C13/0069 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C5/04 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile memory module including a plurality of memory chips and a module controller on a printed circuit board (PCB) may be provided. Each of the plurality of memory chips may include a plurality of nonvolatile memory cell array layers stacked on a substrate in a three dimensional structure. The module controller may control operations of the plurality of memory chips. The module controller may operate each of the plurality of nonvolatile memory cell array layers included in each of the plurality of memory chips in one of a memory mode, in which a corresponding nonvolatile memory cell array layer is used as a working memory area that temporarily stores data for an operation of the nonvolatile memory module, and a storage mode, in which the corresponding nonvolatile memory cell array layer is used as a storage area that preserves data.

公开(公告)号：US20240078034A1

公开(公告)日：2024-03-07

申请号：US18506293

申请日：2023-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G11C7/1063 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C16/0483

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

公开(公告)号：US20170147262A1

公开(公告)日：2017-05-25

申请号：US15297562

申请日：2016-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang-Jin LEE

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0411

Abstract: A nonvolatile memory module including a plurality of memory chips, a spare chip, and a module controller may be provided. The plurality of memory chips may he disposed on a printed circuit board (PCB), and each of the plurality of memory chips may include a plurality of nonvolatile memory cells. The spare chip may be disposed on the PCB and includes a plurality of nonvolatile memory cells. The spare chip may perform different functions according to operation modes of the plurality of memory chips. The module controller may disposed on the PCB, and control operations of the plurality of memory chips and the spare chip.

公开(公告)号：US20210294517A1

公开(公告)日：2021-09-23

申请号：US17231734

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/32 ,  G11C7/10

Abstract: A memory system is provided and includes memory chips in each of which a first state output pin is arranged and a memory controller in which a first state input pin connected to a first channel including first ways respectively connected to the first state output pins arranged in the memory chips is arranged. The memory controller checks a first internal state of each of the memory chips, based on one or more of a chip enable signal and a CE reduction command of the memory chips, and a second signal received through the first state input pin as a result of an AND operation of first signals output through the first state output pins, during a state check interval for checking respective states of the memory chips.

公开(公告)号：US20190324679A1

公开(公告)日：2019-10-24

申请号：US16503116

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-hoon WOO ,  Hak-sun KIM ,  Kwang-Jin LEE ,  Su-chang JEON

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/20 ,  G11C7/20 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: A memory system is provided and includes memory chips and a memory controller. Each of the memory chips one or more first state output pins arranged therein. The memory controller has arranged therein a first state input pin connected in a wired-AND configuration to the one or more first state output pins arranged in the memory chips. The memory controller is configured to transmit a chip enable signal and/or an initially set function command to the memory chips. Each of the memory chips outputs a first state signal having one level from among three logic levels according to a first internal operation state of the memory chip to the one or more first state output pins of the memory chip based on the chip enable signal and/or the initially set function command.