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公开(公告)号:USD877767S1
公开(公告)日:2020-03-10
申请号:US29655465
申请日:2018-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Ju-Hyun Seong , Hee-Jin Ko , A-Hyeon Shim , Seung-Min Lee , Yoo-Jin Choi
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公开(公告)号:US10529865B2
公开(公告)日:2020-01-07
申请号:US15964207
申请日:2018-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joon-Young Kwon , Shin-Young Kim , Yoon-Hwan Son , Jae-Jung Lee , Joon-Sung Kim , Seung-Min Lee
IPC: H01L29/792 , H01L27/11582 , H01L29/66 , H01L27/11565 , H01L27/11575
Abstract: A vertical memory device may include a conductive pattern structure, a pad structure, a plurality of channel structures, a plurality of first dummy structures and a plurality of second dummy structures. The conductive pattern structure may be in a first region of a substrate, and may extend in a first direction. The pad structure may be in a second region of the substrate adjacent to each of opposite sides of the first region of the substrate, and may contact a side of the conductive pattern structure. The channel structures may extend through the conductive pattern structure, and may be regularly arranged on the substrate. The first dummy structures may extend through the conductive pattern structure, and may be disposed in a portion of the first region of the substrate adjacent to the second region thereof. The second dummy structures may extend through the pad structure on the substrate. Each of the channel structures may have a first width in the first direction, and each of the first dummy structures may have a second width in the first direction greater than the first width.
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公开(公告)号:US20180211968A1
公开(公告)日:2018-07-26
申请号:US15923408
申请日:2018-03-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC: H01L27/11565 , H01L27/11582 , H01L21/768 , H01L23/528 , H01L27/11575 , H01L27/11573 , H01L23/544 , H01L27/1157 , H01L23/522
CPC classification number: H01L27/11565 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/544 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2223/5442 , H01L2223/54433 , H01L2223/54453
Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
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公开(公告)号:USD810778S1
公开(公告)日:2018-02-20
申请号:US29582957
申请日:2016-11-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Designer: Hyun-Jee Kwak , Seung-Min Lee , Woo-Seok Hwang , Won-Hee Lee
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公开(公告)号:USD768198S1
公开(公告)日:2016-10-04
申请号:US29534612
申请日:2015-07-30
Applicant: Samsung Electronics Co., Ltd.
Designer: Seung-Min Lee , Min-Hyung Kim
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公开(公告)号:US11120998B2
公开(公告)日:2021-09-14
申请号:US16127443
申请日:2018-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sang-Hyun Lee , Jeon-Il Lee , Sung-Woo Kang , Hong-Sik Shin , Young-Mook Oh , Seung-Min Lee
IPC: H01L21/00 , H01L21/311 , H01L21/768 , H01L21/033 , H01L21/02 , H01L21/8234 , H01L29/49 , H01L29/66 , H01L21/3213 , H01L21/3105 , H01L29/51
Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.
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公开(公告)号:US10398529B2
公开(公告)日:2019-09-03
申请号:US15001895
申请日:2016-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chul-Ho Cho , Kwang-Bok Kim , Seong-Je Cho , Young-Kyu Cho , Seung-Min Lee , Jeong-Gun Lee , Sun-Tae Jung , Jae-Geol Cho
Abstract: A wearable body composition analyzer according to various embodiments of the present disclosure may include an induction part for inducing secretion of bodily liquid while being in contact with a body part, a collection part that collects the bodily liquid secreted, a sensor part that detects a body composition from the bodily liquid collected, and a wearable part to which the induction part and the collection part is detachably attached, wherein the wearable part may be worn on a body. The above-described wearable body composition analyzer may be implemented variously according to embodiments.
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公开(公告)号:USD766979S1
公开(公告)日:2016-09-20
申请号:US29534606
申请日:2015-07-30
Applicant: Samsung Electronics Co., Ltd.
Designer: Seung-Min Lee , Min-Hyung Kim
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公开(公告)号:US11576747B2
公开(公告)日:2023-02-14
申请号:US16459887
申请日:2019-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chul-Ho Cho , Kwang-Bok Kim , Seong-Je Cho , Young-Kyu Cho , Seung-Min Lee , Jeong-Gun Lee , Sun-Tae Jung , Jae-Geol Cho
Abstract: A wearable body composition analyzer according to various embodiments of the present disclosure may include an induction part for inducing secretion of bodily liquid while being in contact with a body part, a collection part that collects the bodily liquid secreted, a sensor part that detects a body composition from the bodily liquid collected, and a wearable part to which the induction part and the collection part is detachably attached, wherein the wearable part may be worn on a body. The above-described wearable body composition analyzer may be implemented variously according to embodiments.
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公开(公告)号:US10304847B2
公开(公告)日:2019-05-28
申请号:US15923408
申请日:2018-03-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seung-Min Lee , Hoo-Sung Cho , Jeong-Seok Nam , Jong-Min Lee , Yong-Joon Choi
IPC: H01L27/11565 , H01L27/11582 , H01L23/544 , H01L27/11573 , H01L27/11575 , H01L23/522 , H01L23/528 , H01L27/1157 , H01L21/768
Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.
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