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    Variable resistance memory devices
    1.
    发明授权
    Variable resistance memory devices 有权
    可变电阻存储器件

    公开(公告)号：US09391269B2

    公开(公告)日：2016-07-12

    申请号：US14457439

    申请日：2014-08-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    IPC分类号： H01L45/00 ,  H01L21/768 ,  H01L27/24 ,  H01L21/336 ,  H01L29/788 ,  H01L27/108

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1675

    摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

    摘要翻译： 可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。

    Variable resistance memory devices and methods of manufacturing the same
    2.
    发明授权
    Variable resistance memory devices and methods of manufacturing the same 有权

    公开(公告)号：US10276793B2

    公开(公告)日：2019-04-30

    申请号：US15595307

    申请日：2017-05-15

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Seung-Jae Jung ,  Youn-Seon Kang

    IPC分类号： H01L27/24 ,  H01L45/00

    摘要： A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.