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公开(公告)号:US10249816B2
公开(公告)日:2019-04-02
申请号:US15996605
申请日:2018-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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公开(公告)号:US10236444B2
公开(公告)日:2019-03-19
申请号:US15432346
申请日:2017-02-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hideki Horii , Seong-Geon Park , Dong-Ho Ahn , Jung-Moo Lee
Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.
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公开(公告)号:US09431458B2
公开(公告)日:2016-08-30
申请号:US14980247
申请日:2015-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jin-Woo Lee , Youn-Seon Kang , Jung-Moo Lee , Seung-Jae Jung , Hyun-Su Ju
CPC classification number: H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
Abstract translation: 半导体器件包括衬底上的第一电极,选择器件图案,可变电阻层图案,第一保护层图案,第二保护层图案和第二电极。 选择装置图案在给定方向上比可变电阻层图案更宽。 第一保护层图案形成在可变电阻层图案的第一对相对侧上。 第二保护层图案形成在可变电阻层图案的第二对相对的第二保护层图案上。 第二电极设置在可变电阻层图案上。
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公开(公告)号:US20190189920A1
公开(公告)日:2019-06-20
申请号:US16277491
申请日:2019-02-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hideki Horii , Seong-Geon Park , Dong-Ho Ahn , Jung-Moo Lee
CPC classification number: H01L45/1683 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144
Abstract: A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.
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公开(公告)号:US10026890B2
公开(公告)日:2018-07-17
申请号:US15177597
申请日:2016-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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公开(公告)号:US09391269B2
公开(公告)日:2016-07-12
申请号:US14457439
申请日:2014-08-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Moo Lee , Youn-Seon Kang , Seung-Jae Jung , Jung-Dal Choi
IPC: H01L45/00 , H01L21/768 , H01L27/24 , H01L21/336 , H01L29/788 , H01L27/108
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/08 , H01L45/1675
Abstract: A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.
Abstract translation: 可变电阻存储器件包括多个第一导线,多个第二导线,多个存储单元,多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。
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公开(公告)号:US09269746B2
公开(公告)日:2016-02-23
申请号:US14323301
申请日:2014-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jin-Woo Lee , Youn-Seon Kang , Jung-Moo Lee , Seung-Jae Jung , Hyun-Su Ju
CPC classification number: H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1675
Abstract: A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
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