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    APPARATUS AND METHOD FOR PREDICTING UPCOMING STAGE OF CAROTID STENOSIS
    1.
    发明申请
    APPARATUS AND METHOD FOR PREDICTING UPCOMING STAGE OF CAROTID STENOSIS 审中-公开
    用于预测CAROTID STENOSIS的最后阶段的装置和方法

    公开(公告)号：US20130274564A1

    公开(公告)日：2013-10-17

    申请号：US13837912

    申请日：2013-03-15

    申请人： SAMSUNG ELECTRONICS CO., LTD. ,  SAMSUNG LIFE WELFARE FOUNDATION

    发明人： Ha-Young Kim ,  Hye-Jin Kam ,  Sang-Hyun Yoo ,  Ji-Hyun Lee ,  Yoonho Choi ,  Mira Kang ,  Jeongeuy Park ,  Jidong Sung ,  Heeyoung Shin ,  Sungwon Cho ,  Soojin Cho

    IPC分类号： A61B5/00 ,  A61B5/02 ,  A61B5/145 ,  A61B8/08 ,  A61B5/0205

    CPC分类号： A61B5/7264 ,  A61B5/02007 ,  A61B5/0205 ,  A61B5/14546 ,  A61B5/7275 ,  A61B8/0891 ,  A61B8/5223 ,  G06F19/3456 ,  G16H50/30

    摘要： An apparatus and a method predict an upcoming stage of carotid stenosis. The apparatus includes a receiving unit, a cluster determining unit, a risk factor score extracting unit, a prediction model storage unit, and a predicting unit. The method includes receiving a patient's medical test data relating to carotid stenosis; determining a cluster to which the patient's medical test data belong based on a gender of the patient; extracting from the patient's medical test data a risk factor score comprising a result of carotid stenosis ultrasonography; storing a plurality of prediction models used to predict an upcoming stage of carotid stenosis; and obtaining an outcome by applying a value indicating a stage of carotid stenosis corresponding to the result of carotid stenosis ultrasonography and the extracted risk factor score to the prediction model corresponding to the determined cluster among the plurality of prediction models.

    摘要翻译： 一种装置和方法预测即将到来的颈动脉狭窄期。 该装置包括接收单元，群集确定单元，风险因子得分提取单元，预测模型存储单元和预测单元。 该方法包括接收患者关于颈动脉狭窄的医学检查数据; 基于患者的性别确定患者的医学检查数据所属的群集; 从患者的医学检验数据中提取包括颈动脉狭窄超声检查结果的危险因素评分; 存储用于预测即将到来的颈动脉狭窄期的多个预测模型; 通过将与颈动脉狭窄超声检查结果相对应的颈动脉狭窄阶段的值和所提取的风险因子得分应用于与所述多个预测模型中的所确定的群集对应的预测模型来获得结果。

    APPARATUS AND METHOD FOR PREDICTING POTENTIAL DEGREE OF CORONARY ARTERY CALCIFICATION (CAC) RISK
    4.
    发明申请
    APPARATUS AND METHOD FOR PREDICTING POTENTIAL DEGREE OF CORONARY ARTERY CALCIFICATION (CAC) RISK 审中-公开
    用于预测冠状动脉计算（CAC）风险潜在程度的装置和方法

    公开(公告)号：US20130275154A1

    公开(公告)日：2013-10-17

    申请号：US13834150

    申请日：2013-03-15

    申请人： SAMSUNG ELECTRONICS CO., LTD. ,  SAMSUNG LIFE WELFARE FOUNDATION

    发明人： Hye-Jin Kam ,  Ha-Young Kim ,  Sang-Hyun Yoo ,  Ji-Hyun Lee ,  Yoonho Choi ,  Mira Kang ,  Jeongeuy Park ,  Jidong Sung ,  Heeyoung Shin ,  Sungwon Cho ,  Soojin Cho

    IPC分类号： G06F19/00 ,  G06Q50/24

    CPC分类号： G16H50/30 ,  G06Q50/24

    摘要： A method of predicting a potential degree of Coronary Artery Calcification (CAC) risk includes receiving a patient's medical test data relating to CAC; determining a cluster to which the patient's medical test data belong based on an age of the patient; extracting a risk factor score including at least two Coronary Artery Calcification Scores (CACSs) from the medical test data; storing a plurality of prediction models used for predicting a potential degree of CAC risk; and predicting a potential degree of CAC risk at a specific point in time by applying a CACS growth rate of the patient's medical test data calculated using the at least two CACSs of the patient's medical test data and the extracted risk factor score to a prediction model corresponding to the determined cluster to which the patient's medical test data belong among the plurality of prediction models.

    摘要翻译： 预测冠状动脉钙化（CAC）风险潜在程度的方法包括接收患者与CAC有关的医学检验数据; 基于患者的年龄确定患者的医学测试数据所属的群集; 从医疗测试数据中提取包括至少两个冠状动脉钙化积分（CACS）的风险因子得分; 存储用于预测潜在的CAC风险程度的多个预测模型; 并且通过将使用患者医疗测试数据的至少两个CACS计算的患者的医疗测试数据的CACS增长率和所提取的危险因素得分应用到对应的预测模型来预测在特定时间点的CAC风险的潜在程度 到患者的医学测试数据属于多个预测模型中的确定的群集。

    System on chip
    6.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC分类号： H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    摘要： Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    摘要翻译： 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11387255B2

    公开(公告)日：2022-07-12

    申请号：US16989160

    申请日：2020-08-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jintae Kim ,  Ha-Young Kim ,  Sinwoo Kim ,  Moo-Gyu Bae ,  Jaeha Lee

    IPC分类号： H01L27/11597 ,  H01L27/108 ,  H01L27/11524 ,  H01L27/06

    摘要： Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

    Semiconductor device including standard cell
    8.
    发明授权
    Semiconductor device including standard cell 有权

    公开(公告)号：US11355489B2

    公开(公告)日：2022-06-07

    申请号：US17009941

    申请日：2020-09-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Byounggon Kang ,  Subin Jin ,  Ha-Young Kim

    IPC分类号： H01L27/02 ,  H03K3/3562 ,  H03K3/037 ,  H01L27/118

    摘要： A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

    System on chip
    9.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    摘要： A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11699992B2

    公开(公告)日：2023-07-11

    申请号：US16726379

    申请日：2019-12-24

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

    IPC分类号： H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

    CPC分类号： H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

    摘要： A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.