公开(公告)号：US20220036953A1

公开(公告)日：2022-02-03

申请号：US17221833

申请日：2021-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin JOE ,  Sangsoo PARK ,  Joonsuc JANG ,  Kihoon KANG ,  Yonghyuk CHOI

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.

公开(公告)号：US20220254433A1

公开(公告)日：2022-08-11

申请号：US17469422

申请日：2021-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung KIM ,  Youngdeok SEO ,  Dongmin SHIN ,  Joonsuc JANG ,  Sungmin JOE

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C16/26 ,  G11C29/12

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.

公开(公告)号：US20220157393A1

公开(公告)日：2022-05-19

申请号：US17530586

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Junyong PARK ,  Hyunggon KIM ,  Byungsoo Kim ,  Sungmin JOE

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C11/56 ,  G11C16/10 ,  H01L27/11582 ,  G06F3/06

Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

公开(公告)号：US20240145016A1

公开(公告)日：2024-05-02

申请号：US18400297

申请日：2023-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyong PARK ,  Hyunggon KIM ,  Byungsoo KIM ,  Sungmin JOE

IPC: G11C16/34 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H10B43/27

CPC classification number: G11C16/3459 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H10B43/27 ,  G11C2211/5621

Abstract: A method for programming at least one memory cell of a plurality of memory cells included in a non-volatile memory device, the at least one memory cell including a word line and a bit line, the method including: performing a first and second program and verify operation based on a first and second condition, respectively, wherein each program and verify operation includes generating a program voltage and a bit line voltage by a voltage generator included in the non-volatile memory device and providing the program voltage and the bit line voltage to the word line and the bit line, respectively, wherein voltage levels and voltage application times of each program voltage and bit line voltage correspond to the first condition or the second condition, respectively, wherein the first condition is different from the second condition.

公开(公告)号：US20230124303A1

公开(公告)日：2023-04-20

申请号：US18068337

申请日：2022-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung KIM ,  Youngdeok SEO ,  Dongmin SHIN ,  Joonsuc JANG ,  Sungmin JOE

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C16/10 ,  G11C29/12 ,  G11C16/26

Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.