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公开(公告)号：US20240290399A1
公开(公告)日：2024-08-29
申请号：US18495210
申请日：2023-10-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsoo KIM , Jinsu KIM , Hyunggon KIM
CPC classification number: G11C16/3427 , G11C16/08 , G11C16/30
Abstract: A flash memory comprises a memory cell array having a plurality of memory cells; a read recovery voltage generator configured to provide a read recovery voltage to the plurality of memory cells; and a read recovery voltage controller configured to provide recovery control signals for controlling the read recovery voltage. The read recovery voltage generator includes a plurality of ground pass transistors that during a read recovery operation are configured to control a falling slope of an unselection recovery voltage provided to an unselected word line in response to the recovery control signals.
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公开(公告)号：US20240194269A1
公开(公告)日：2024-06-13
申请号：US18517429
申请日：2023-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungsoo KIM , Yohan LEE , Hyunggon KIM , Sang Soo PARK , Bongsoon LIM , Jin-Young CHUN
CPC classification number: G11C16/16 , G11C16/0483
Abstract: A memory device includes a memory cell array having a plurality of memory blocks therein, including a target memory block. A voltage generator is provided, which is configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed. Control logic is provided, which is configured to control the memory cell array and the voltage generator. In addition, during operation, the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block, and a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block.
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公开(公告)号：US20220281465A1
公开(公告)日：2022-09-08
申请号：US17684738
申请日：2022-03-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaewoong LEE , Hyunggon KIM , Woong LEE , Yuseon LEE , Changwon JANG
IPC: B60W50/00 , B60W60/00 , G07C5/00 , B60W40/105 , G01C21/36
Abstract: An electronic apparatus is disclosed, including a memory, communication circuitry, and a processor. The processor implements the method, including: identifying a state of the communication connection with the external server, based on the identified state, determining a target size for data to be transmitted to the external server, controlling at least one sensor of the vehicle to collect the data such that a total size of the collected data is less than or equal to the determined target size, transmitting the data collected by the at least one sensor to the external server, and receiving a control command from the external server based on the transmitted data, and control a function of the vehicle according to the received control command.
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4.发明申请公开(公告)号：US20220013184A1
公开(公告)日：2022-01-13
申请号：US17336910
申请日：2021-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Garam KIM , Hyunggon KIM , Jisang LEE , Joonsuc JANG , Wontaeck JUNG
Abstract: A memory device includes a memory cell array including a plurality of memory cells; a voltage generator configured to generate voltages used for a program operation and a verify operation for the memory cells; and control logic configured to perform a plurality of program loops while writing data to the memory cell array, such that first to N-th (e.g., N>=1) program loops including a program operation and a verify operation are performed and at least two program loops in which the verify operation is skipped are performed when a pass/fail determination of the program operation in the N-th program loop indicates a pass.
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5.发明公开公开(公告)号：US20240277226A1
公开(公告)日：2024-08-22
申请号：US18650981
申请日：2024-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chungsoon PARK , Kyungmin KIM , Sujin PARK , Hyunggon KIM
CPC classification number: A61B5/0017 , A61B5/0059 , H02J7/00045 , H02J7/0047 , H02J7/04 , H02J50/12 , H02J50/20 , H02J50/80 , H04B10/502 , H04B10/69 , A61B2562/0233
Abstract: An electronic device is provided comprising: a biometric sensor, including at least one light emitting diode (LED) and at least one light receiving unit, for acquiring biometric information by means of the at least one light emitting device and the at least one light receiving unit; a power receiving circuit configured to receive a wireless power signal from an external electronic device; and a processor operatively coupled to the biometric sensor and the power receiving circuit. The processor may be configured to receive a designated wireless power signal from the external electronic device by using the power receiving circuit and to perform optical communication with the external electronic device by using the biosensor when the designated wireless power signal is received. Other various embodiments identified from the specification are also possible.
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Patent Agency Ranking
公开(公告)号：US20230223688A1
公开(公告)日：2023-07-13
申请号：US18179776
申请日：2023-03-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunggon KIM , Seungjin YU , Woong LEE , Yuseon LEE , Jaewoong LEE , Changwon JANG , Seungbum JU
CPC classification number: H01Q3/36 , H01Q3/28 , H01Q3/2694 , H01Q1/32
Abstract: A vehicle antenna apparatus is provided. The vehicle antenna apparatus includes an array antenna including a plurality of antenna elements that output a plurality of beams identified by output directions, and a processor configured to perform at least one instruction. The processor is further configured to obtain speed information of a vehicle, select at least one beam from among the plurality of beams such that a shape of a beam pattern formed by the plurality of beams is changed based on the speed information, and control the array antenna to output the selected beam.
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公开(公告)号：US20230123963A1
公开(公告)日：2023-04-20
申请号：US18067224
申请日：2022-12-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minseok KIM , Hyunggon KIM
Abstract: A non-volatile memory device receives a read command and an address from a controller, and performs a data recovery read operation in response to the read command. In the data recovery read operation, an operation of obtaining aggressor group information from a memory cell connected to a word line adjacent to a word line selected according to the address, and an operation of recovering data corresponding to the obtained aggressor group information in a memory cell connected to the word line selected according to the address, are repeatedly performed on each of a plurality of aggressor groups.
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公开(公告)号：US20230027955A1
公开(公告)日：2023-01-26
申请号：US17697386
申请日：2022-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon LIM , Hyunggon KIM
IPC: H01L27/11582 , H01L27/11573 , G11C16/04 , G11C16/06
Abstract: A non-volatile memory device includes a memory cell region and a peripheral circuit region below the memory cell region in a vertical direction. The memory cell region includes an upper substrate, channel structures extending in the vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction and a first via structure on the first lower metal line and a second via structure on the first lower metal line, a top surface of the second via being in contact with the upper substrate. The memory cell region further includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.
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公开(公告)号：US20220157381A1
公开(公告)日：2022-05-19
申请号：US17483088
申请日：2021-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minseok KIM , Joonsuc JANG , Hyunggon KIM , Seonyong LEE
Abstract: A method of operating a memory device, the method including: performing a first program operation to form a plurality of first threshold voltage distributions; and performing a second program operation by using a coarse verification voltage and a fine verification voltage based on offset information to form a plurality of second threshold voltage distributions respectively corresponding to a plurality of program states from the plurality of first threshold voltage distributions, wherein the offset information includes a plurality of offsets that vary according to characteristics of the second threshold voltage distributions.
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公开(公告)号：US20240170048A1
公开(公告)日：2024-05-23
申请号：US18219369
申请日：2023-07-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youse KIM , Hyunggon KIM , Bongsoon LIM
IPC: G11C11/4093 , G11C11/408
CPC classification number: G11C11/4093 , G11C11/4085 , G11C11/4087
Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, bit-lines and a memory cell array which includes one or more memory blocks spaced apart from each other, one or more dummy blocks between the one or more memory blocks and a through-hole via region. The second semiconductor layer is under the first semiconductor layer includes a control circuit. The control circuit divides each of the one or more dummy blocks into an adjacent sub-block directly contacting the through-hole via region and a non-adjacent sub-block based on a relative distance from the through-hole via region in the first direction and uses each of the non-adjacent sub-blocks as a sub-block to store data.
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