公开(公告)号：US09934858B2

公开(公告)日：2018-04-03

申请号：US14700500

申请日：2015-04-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Niles Yang ,  Rohit Sehgal ,  Abhilash Kashyap

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/28 ,  G11C7/14 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: In a non-volatile memories formed according to a NAND type of architecture, one or more of the end word lines on the source end, drain end, or both are set aside as dummy word lines that are not used to store user data. In addition to the host data, a memory system typically also stores metadata, or information about the user data, how it is stored and the memory system itself. Techniques are presented for using the dummy word lines of the memory blocks to hold this metadata. This arrangement allows for the metadata of a memory block to be known in real time, without reducing the storage capacity of the memory system.

公开(公告)号：US10025661B1

公开(公告)日：2018-07-17

申请号：US15391455

申请日：2016-12-27

Applicant: SanDisk Technologies LLC

Inventor： Pitamber Shukla ,  Joanna Lai ,  Henry Chin ,  Deepak Raghu ,  Abhilash Kashyap

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/28 ,  G11C16/10

Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.

公开(公告)号：US20180181462A1

公开(公告)日：2018-06-28

申请号：US15391455

申请日：2016-12-27

Applicant: SanDisk Technologies LLC

Inventor： Pitamber Shukla ,  Joanna Lai ,  Henry Chin ,  Deepak Raghu ,  Abhilash Kashyap

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/28 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0407

Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.