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    POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS
    2.
    发明申请
    POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS 有权

    公开(公告)号：US20230005539A1

    公开(公告)日：2023-01-05

    申请号：US17943550

    申请日：2022-09-13

    Applicant: SanDisk Technologies LLC

    Inventor： Neil Robertson ,  Michael Grobis ,  Ward Parkinson

    IPC: G11C13/00

    Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

    MULTI-LEVEL ULTRA-LOW POWER INFERENCE ENGINE ACCELERATOR
    3.
    发明申请
    MULTI-LEVEL ULTRA-LOW POWER INFERENCE ENGINE ACCELERATOR 有权

    公开(公告)号：US20220108759A1

    公开(公告)日：2022-04-07

    申请号：US17061820

    申请日：2020-10-02

    Applicant: SanDisk Technologies LLC

    Inventor： Michael Nicolas Albert Tran ,  Michael Grobis

    IPC: G11C17/18 ,  G11C11/54 ,  G11C17/16 ,  G06N3/08

    Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.

    Concurrent write to programmable resistance memory cells in cross-point array
    4.
    发明授权
    Concurrent write to programmable resistance memory cells in cross-point array 有权

    公开(公告)号：US12205638B2

    公开(公告)日：2025-01-21

    申请号：US17939818

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

    IPC: G11C11/56 ,  G11C11/16 ,  H01L23/00 ,  H01L25/065 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

    PROGRAMMABLE ECC FOR MRAM MIXED-READ SCHEME
    6.
    发明申请
    PROGRAMMABLE ECC FOR MRAM MIXED-READ SCHEME 有权

    公开(公告)号：US20230101414A1

    公开(公告)日：2023-03-30

    申请号：US17552143

    申请日：2021-12-15

    Applicant: SanDisk Technologies LLC

    Inventor： Martin Hassner ,  Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin ,  Raj Ramanujan

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C29/12

    Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

    POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS
    7.
    发明申请
    POWER OFF RECOVERY IN CROSS-POINT MEMORY WITH THRESHOLD SWITCHING SELECTORS 有权

    公开(公告)号：US20220139454A1

    公开(公告)日：2022-05-05

    申请号：US17090438

    申请日：2020-11-05

    Applicant: SanDisk Technologies LLC

    Inventor： Neil Robertson ,  Michael Grobis ,  Ward Parkinson

    IPC: G11C13/00

    Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

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